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From: Conor Dooley <conor@kernel.org>
To: Friday Yang <friday.yang@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Garmin Chang <garmin.chang@mediatek.com>,
	Yong Wu <yong.wu@mediatek.com>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v4 1/2] dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
Date: Fri, 21 Feb 2025 16:57:12 +0000	[thread overview]
Message-ID: <20250221-cavalier-property-7e7eceba7bc6@spud> (raw)
In-Reply-To: <20250221075058.14180-2-friday.yang@mediatek.com>

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On Fri, Feb 21, 2025 at 03:50:53PM +0800, Friday Yang wrote:
> On the MediaTek platform, some SMI LARBs are directly connected to
> the SMI Common, while others are connected to the SMI Sub-Common,
> which in turn is connected to the SMI Common. The hardware block
> diagram can be described as follows.
> 
>              SMI-Common(Smart Multimedia Interface Common)
>                  |
>          +----------------+------------------+
>          |                |                  |
>          |                |                  |
>          |                |                  |
>          |                |                  |
>          |                |                  |
>        larb0       SMI-Sub-Common0     SMI-Sub-Common1
>                    |      |     |      |             |
>                   larb1  larb2 larb3  larb7       larb9
> 
> For previous discussion on the direction of the code modifications,
> please refer to:
> https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=
> wXpobDWU1CnvkA@mail.gmail.com/
> https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey
> hP+KJ5Fasm2rFg@mail.gmail.com/
> 
> On the MediaTek MT8188 SoC platform, we encountered power-off failures
> and SMI bus hang issues during camera stress tests. The issue arises
> because bus glitches are sometimes produced when MTCMOS powers on or
> off. While this is fairly normal, the software must handle these
> glitches to avoid mistaking them for transaction signals. What's
> more, this issue emerged only after the initial upstreaming of this
> binding. Without these patches, the SMI becomes unstable during camera
> stress tests.
> 
> The software solutions can be summarized as follows:
> 
> 1. Use CLAMP to disable the SMI sub-common port after turning off the
>    LARB CG and before turning off the LARB MTCMOS.
> 2. Use CLAMP to disable/enable the SMI sub-common port.
> 3. Implement an AXI reset for SMI LARBs.
> 
> This patch add '#reset-cells' for the clock controller located in image,
> camera and IPE subsystems.
> 
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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  reply	other threads:[~2025-02-21 16:57 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-21  7:50 [PATCH v4 0/2] Add SMI LARBs reset for MediaTek MT8188 SoC Friday Yang
2025-02-21  7:50 ` [PATCH v4 1/2] dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 Friday Yang
2025-02-21 16:57   ` Conor Dooley [this message]
2025-02-24  8:42   ` AngeloGioacchino Del Regno
2025-02-27 22:32   ` Stephen Boyd
2025-02-21  7:50 ` [PATCH v4 2/2] clk: " Friday Yang
2025-02-24  8:42   ` AngeloGioacchino Del Regno
2025-02-27 22:32   ` Stephen Boyd

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