[PATCH v9 1/3] dt-binding: clock: ast2700: modify soc0/1 clock define

Ryan Chen
2025-02-24T09:55:12Z

-remove redundant SOC0_CLK_UART_DIV13:
SOC0_CLK_UART_DIV13 is not use at clk-ast2700.c, the clock
source tree is uart clk src -> uart_div_table -> uart clk.

-Change SOC0_CLK_HPLL_DIV_AHB to SOC0_CLK_AHBMUX:
modify clock tree implement.
older CLK_AHB use mpll_div_ahb/hpll_div_ahb to be ahb clock source.
mpll->mpll_div_ahb
-> clk_ahb
hpll->hpll_div_ahb

new use SOC0_CLK_AHBMUX for more understand clock source divide tree.
mpll->
ahb_mux -> div_table -> clk_ahb
hpll->

-new add clock:
SOC0_CLK_MPHYSRC: UFS MPHY clock source.
SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source.
SOC1_CLK_I3C: I3C clock source.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
include/dt-bindings/clock/aspeed,ast2700-scu.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/include/dt-bindings/clock/aspeed,ast2700-scu.h b/include/dt-bindings/clock/aspeed,ast2700-scu.h
index 63021af3caf5..c7389530629d 100644
--- a/include/dt-bindings/clock/aspeed,ast2700-scu.h
+++ b/include/dt-bindings/clock/aspeed,ast2700-scu.h
@@ -13,18 +13,17 @@
#define SCU0_CLK_24M 1
#define SCU0_CLK_192M 2
#define SCU0_CLK_UART 3
-#define SCU0_CLK_UART_DIV13 3
#define SCU0_CLK_PSP 4
#define SCU0_CLK_HPLL 5
#define SCU0_CLK_HPLL_DIV2 6
#define SCU0_CLK_HPLL_DIV4 7
-#define SCU0_CLK_HPLL_DIV_AHB 8
+#define SCU0_CLK_AHBMUX 8
#define SCU0_CLK_DPLL 9
#define SCU0_CLK_MPLL 10
#define SCU0_CLK_MPLL_DIV2 11
#define SCU0_CLK_MPLL_DIV4 12
#define SCU0_CLK_MPLL_DIV8 13
-#define SCU0_CLK_MPLL_DIV_AHB 14
+#define SCU0_CLK_MPHYSRC 14
#define SCU0_CLK_D0 15
#define SCU0_CLK_D1 16
#define SCU0_CLK_CRT0 17
@@ -68,6 +67,7 @@
#define SCU0_CLK_GATE_UFSCLK 53
#define SCU0_CLK_GATE_EMMCCLK 54
#define SCU0_CLK_GATE_RVAS1CLK 55
+#define SCU0_CLK_U2PHY_REFCLKSRC 56

/* SOC1 clk */
#define SCU1_CLKIN 0
@@ -160,4 +160,5 @@
#define SCU1_CLK_GATE_PORTDUSB2CLK 85
#define SCU1_CLK_GATE_LTPI1TXCLK 86

+#define SCU1_CLK_I3C 87
#endif
--
2.34.1