[PATCH 3/3] riscv: dts: sophgo: add Sophgo SPI NOR controller driver

Longbin Li
2025-02-24T10:13:10Z

Add SPI NOR device node for Sophgo.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
---
.../boot/dts/sophgo/sg2044-sophgo-sd3-10.dts | 18 ++++++++++++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 +++++++++++++++++++
2 files changed, 42 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-sd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-sd3-10.dts
index c50e61a50013..9c634920f37e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-sd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-sd3-10.dts
@@ -80,6 +80,24 @@ &sd {
status = "okay";
};

+&spifmc0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ };
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index 6eaf92dd0a90..e45f7218de04 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -33,6 +33,30 @@ soc {
dma-noncoherent;
ranges;

+ spifmc0: spi@7001000000 {
+ compatible = "sophgo,sg2044-spifmc-nor";
+ reg = <0x70 0x01000000 0x0 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_AHB_SPIFMC>;
+ interrupt-parent = <&intc>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPIFMC0>;
+ status = "disabled";
+ };
+
+ spifmc1: spi@7005000000 {
+ compatible = "sophgo,sg2044-spifmc-nor";
+ reg = <0x70 0x05000000 0x0 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_AHB_SPIFMC>;
+ interrupt-parent = <&intc>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPIFMC1>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@7020000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x70 0x20000000 0x0 0x10000>;
--
2.48.1