Re: [PATCH AUTOSEL 6.13 32/32] irqchip/qcom-pdc: Workaround hardware register bug on X1E80100

Sasha Levin
2025-03-15T01:30:41Z

On Mon, Feb 24, 2025 at 03:46:04PM +0100, Johan Hovold wrote:
>Hi Sasha,
>
>On Mon, Feb 24, 2025 at 06:16:38AM -0500, Sasha Levin wrote:
>> From: Stephan Gerhold <stephan.gerhold@linaro.org>
>>
>> [ Upstream commit e9a48ea4d90be251e0d057d41665745caccb0351 ]
>>
>> On X1E80100, there is a hardware bug in the register logic of the
>> IRQ_ENABLE_BANK register: While read accesses work on the normal address,
>> all write accesses must be made to a shifted address. Without a workaround
>> for this, the wrong interrupt gets enabled in the PDC and it is impossible
>> to wakeup from deep suspend (CX collapse). This has not caused problems so
>> far, because the deep suspend state was not enabled. A workaround is
>> required now since work is ongoing to fix this.
>
>> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
>> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
>> Tested-by: Johan Hovold <johan+linaro@kernel.org>
>> Link: https://lore.kernel.org/all/20250218-x1e80100-pdc-hw-wa-v2-1-29be4c98e355@linaro.org
>> Signed-off-by: Sasha Levin <sashal@kernel.org>
>
>This one was not marked for backporting on purpose and is not needed in
>older kernels, please drop from all autosel queues.

Will do, thanks!

--
Thanks,
Sasha