Re: [Patch v2 12/24] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR

[Peter Zijlstra <peterz@infradead.org>]

On Tue, Feb 18, 2025 at 03:28:06PM +0000, Dapeng Mi wrote:
> Arch-PEBS introduces a new MSR IA32_PEBS_BASE to store the arch-PEBS
> buffer physical address. This patch allocates arch-PEBS buffer and then
> initialize IA32_PEBS_BASE MSR with the buffer physical address.

Not loving how this patch obscures the whole DS area thing and naming.


> @@ -624,13 +604,18 @@ static int alloc_pebs_buffer(int cpu)
>  	int max, node = cpu_to_node(cpu);
>  	void *buffer, *insn_buff, *cea;
>  
> -	if (!x86_pmu.ds_pebs)
> +	if (!intel_pmu_has_pebs())
>  		return 0;
>  
> -	buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
> +	buffer = dsalloc_pages(bsiz, preemptible() ? GFP_KERNEL : GFP_ATOMIC, cpu);

But this plain smells bad, what is this about?

>  	if (unlikely(!buffer))
>  		return -ENOMEM;
>  
> +	if (x86_pmu.arch_pebs) {
> +		hwev->pebs_vaddr = buffer;
> +		return 0;
> +	}
> +
>  	/*
>  	 * HSW+ already provides us the eventing ip; no need to allocate this
>  	 * buffer then.