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Thu, 27 Feb 2025 16:40:18 +0100 From: Christophe Parant To: , , , CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Subject: [PATCH 11/11] ARM: dts: stm32: phyboard-sargas and phycore: Add optional interfaces Date: Thu, 27 Feb 2025 16:40:12 +0100 Message-ID: <20250227154012.259566-12-c.parant@phytec.fr> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250227154012.259566-1-c.parant@phytec.fr> References: <20250227154012.259566-1-c.parant@phytec.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 27.02.2025 16:40:18, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 27.02.2025 16:40:18 X-TNEFEvaluated: 1 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM2PEPF0001C70C:EE_|DB9P195MB2156:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c367ded-1fc8-4af1-d43d-08dd57451943 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2025 15:40:44.4401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c367ded-1fc8-4af1-d43d-08dd57451943 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C70C.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9P195MB2156 - stm32mp15xx-phycore-som: add NAND device on FMC interface to support the SoM version equipped with NAND flash instead of eMMC. - stm32mp15xx-phyboard-sargas: define pinctrl for PWM5, LTDC and DCMI interfaces used on phyBOARD-Sargas. Those interfaces are not enabled by default as PHYTEC displays and PHYTEC cameras are enabled and configured throught device tree overlays. PWM5 is used for LCD backlight command. Signed-off-by: Christophe Parant --- .../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 23 +++++++++++++++++++ .../boot/dts/st/stm32mp15xx-phycore-som.dtsi | 16 +++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index 729a97f82538..2f351adc5986 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -260,3 +260,26 @@ &usbphyc=5Fport0 { &usbphyc=5Fport1 { phy-supply =3D <&vdd=5Fusb>; }; + +&timers5 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm5: pwm { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pwm5=5Fpins=5Fc>; + pinctrl-1 =3D <&pwm5=5Fsleep=5Fpins=5Fc>; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc=5Fpins=5Ff>; + pinctrl-1 =3D <<dc=5Fsleep=5Fpins=5Ff>; +}; + +&dcmi { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&dcmi=5Fpins=5Fd>; + pinctrl-1 =3D <&dcmi=5Fsleep=5Fpins=5Fd>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index 0689967b8c56..23db635c39a1 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -345,3 +345,19 @@ &sdmmc2 { st,neg-edge; status =3D "disabled"; }; + +&fmc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&fmc=5Fpins=5Fa>; + pinctrl-1 =3D <&fmc=5Fsleep=5Fpins=5Fa>; + status =3D "disabled"; + + nand-controller@4,0 { + nand0: nand@0 { + reg =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; + }; +}; --=20 2.34.1