From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: x86@kernel.org, Tony Luck <tony.luck@intel.com>,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early()
Date: Fri, 28 Feb 2025 09:29:53 -0500 [thread overview]
Message-ID: <20250228142953.GA1053941@yaz-khff2.amd.com> (raw)
In-Reply-To: <7D626975-3F9C-4B7F-A1E7-FAB3B02964DC@alien8.de>
On Thu, Feb 27, 2025 at 09:48:01PM +0100, Borislav Petkov wrote:
> On February 27, 2025 8:59:33 PM GMT+01:00, Yazen Ghannam <yazen.ghannam@amd.com> wrote:
> >On Thu, Feb 27, 2025 at 08:33:19PM +0100, Borislav Petkov wrote:
> >> On February 27, 2025 5:31:48 PM GMT+01:00, Yazen Ghannam <yazen.ghannam@amd.com> wrote:
> >> >On Thu, Feb 27, 2025 at 04:25:00PM +0100, Borislav Petkov wrote:
> >> >> On Thu, Feb 13, 2025 at 04:45:55PM +0000, Yazen Ghannam wrote:
> >> >> > Also, move __mcheck_cpu_init_generic() after
> >> >> > __mcheck_cpu_init_prepare_banks() so that MCA is enabled after the first
> >> >> > MCA polling event.
> >> >>
> >> >> The reason being?
> >> >>
> >> >> Precaution?
> >> >>
> >> >> It was this way since forever, why are you moving it now? Any particular
> >> >> reason?
> >> >>
> >> >
> >> >1) To read/clear old errors before turning on MCA. The updated
> >> >__mcheck_cpu_init_prepare_banks() function does this for the MCi_CTL
> >> >registers. This patch does this for the MCG_CTL register too.
> >> >
> >> >2) To ensure that vendor-specific setup is finished beforehand also.
> >>
> >> That doesn't answer my question. All of the above gets done even without shuffling the order...
> >>
> >>
> >
> >MCA banks can start logging errors once MCG_CTL is set. The AMD docs say
> >"The operating system must initialize the MCA_CONFIG registers prior to
> >initialization of the MCA_CTL registers."
> >
> >"The MCA_CTL registers must be initialized prior to enabling the error
> >reporting banks in MCG_CTL".
> >
> >However, the Intel docs "Machine-Check Initialization Pseudocode" say
> >MCG_CTL first then MCi_CTL.
> >
> >But both agree that CR4.MCE should be set last.
> >
> >We have an old thread on the topic that led to this patch.
> >https://lore.kernel.org/all/YqJHwXkg3Ny9fI3s@yaz-fattaah/
> >
> >And it seemed okay at the time.
> >https://lore.kernel.org/all/YrnTMmwl5TrHwT9J@zn.tnic/
> >
> >I don't think anything much has changed since then, so I included the
> >old patch again in this set.
> >
> >Thanks,
> >Yazen
>
> This is exactly what needs to be in the commit message - why is the change being done.
> --
Sure thing. I'll update the commit message.
Thanks,
Yazen
next prev parent reply other threads:[~2025-02-28 14:29 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 16:45 [PATCH v2 00/16] AMD MCA interrupts rework Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 01/16] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-02-17 6:58 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 02/16] x86/mce/amd: Remove return value for mce_threshold_create_device() Yazen Ghannam
2025-02-17 7:11 ` Zhuo, Qiuxu
2025-02-17 14:09 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-02-17 7:57 ` Zhuo, Qiuxu
2025-02-17 14:17 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 04/16] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-02-18 1:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 05/16] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-02-13 22:32 ` Luck, Tony
2025-02-17 13:55 ` Yazen Ghannam
2025-02-18 16:40 ` Luck, Tony
2025-02-18 2:15 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-02-18 3:00 ` Zhuo, Qiuxu
2025-02-19 15:53 ` Yazen Ghannam
2025-02-27 15:25 ` Borislav Petkov
2025-02-27 16:31 ` Yazen Ghannam
2025-02-27 19:33 ` Borislav Petkov
2025-02-27 19:59 ` Yazen Ghannam
2025-02-27 20:48 ` Borislav Petkov
2025-02-28 14:29 ` Yazen Ghannam [this message]
2025-02-13 16:45 ` [PATCH v2 07/16] x86/mce: Define BSP-only init Yazen Ghannam
2025-02-18 3:16 ` Zhuo, Qiuxu
2025-02-19 15:57 ` Yazen Ghannam
2025-02-20 1:37 ` Zhuo, Qiuxu
2025-02-20 14:36 ` Yazen Ghannam
2025-02-24 13:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-02-18 3:33 ` Zhuo, Qiuxu
2025-02-19 16:01 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 09/16] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-02-18 5:31 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 10/16] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-02-18 6:03 ` Zhuo, Qiuxu
2025-02-19 16:06 ` Yazen Ghannam
2025-02-20 1:27 ` Zhuo, Qiuxu
2025-02-20 14:37 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-02-18 6:29 ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-02-18 6:42 ` Zhuo, Qiuxu
2025-02-19 16:07 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 13/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-02-18 7:37 ` Zhuo, Qiuxu
2025-02-19 16:09 ` Yazen Ghannam
2025-02-20 1:41 ` Zhuo, Qiuxu
2025-02-20 14:41 ` Yazen Ghannam
2025-02-24 13:31 ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 14/16] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-02-18 8:23 ` Zhuo, Qiuxu
2025-02-19 16:16 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-02-13 22:34 ` Luck, Tony
2025-02-17 14:06 ` Yazen Ghannam
2025-02-18 13:27 ` Zhuo, Qiuxu
2025-02-19 16:19 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-02-18 13:51 ` Zhuo, Qiuxu
2025-02-13 22:40 ` [PATCH v2 00/16] AMD MCA interrupts rework Luck, Tony
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