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[142.68.128.5]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e8976da283sm25082546d6.111.2025.02.28.11.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 11:32:22 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1to65t-00000000Th1-2Pej; Fri, 28 Feb 2025 15:32:21 -0400 Date: Fri, 28 Feb 2025 15:32:21 -0400 From: Jason Gunthorpe To: =?utf-8?Q?Miko=C5=82aj?= Lenczewski , Shameer Kolothum Cc: ryan.roberts@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, joro@8bytes.org, jean-philippe@linaro.org, mark.rutland@arm.com, joey.gouly@arm.com, oliver.upton@linux.dev, james.morse@arm.com, broonie@kernel.org, maz@kernel.org, david@redhat.com, akpm@linux-foundation.org, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev Subject: Re: [PATCH v2 4/4] iommu/arm: Add BBM Level 2 smmu feature Message-ID: <20250228193221.GM5011@ziepe.ca> References: <20250228182403.6269-2-miko.lenczewski@arm.com> <20250228182403.6269-6-miko.lenczewski@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250228182403.6269-6-miko.lenczewski@arm.com> On Fri, Feb 28, 2025 at 06:24:04PM +0000, Mikołaj Lenczewski wrote: > For supporting BBM Level 2 for userspace mappings, we want to ensure > that the smmu also supports its own version of BBM Level 2. Luckily, the > smmu spec (IHI 0070G 3.21.1.3) is stricter than the aarch64 spec (DDI > 0487K.a D8.16.2), so already guarantees that no aborts are raised when > BBM level 2 is claimed. > > Add the feature and testing for it under arm_smmu_sva_supported(). > > Signed-off-by: Mikołaj Lenczewski > --- > arch/arm64/kernel/cpufeature.c | 7 +++---- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 3 +++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ > 4 files changed, 13 insertions(+), 4 deletions(-) This patch looks good, for what it does. However for bisection safety it should be earlier, before the patches that change the page table algorithms to be unsafe for the SMMU. However, I've heard people talking about shipping chips that have CPUs with BBML2 but SMMUs without. On such a system it seems like your series would break previously working SVA support because this patch will end up disabling it? Though I see your MIDR_REV list is limited, so perhaps that worry doesn't effect any real chips made with those families? I am trying to check some NVIDIA products against this list.. Jason