Re: [PATCH 3/9] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver

Jonathan Cameron
2025-03-04T09:27:53Z

On Tue, 18 Feb 2025 17:19:54 +0800
Yicong Yang <yangyicong@huawei.com> wrote:

> From: Junhao He <hejunhao3@huawei.com>
>
> HiSilicon DDRC v3 PMU has the different interrupt register offset
> compared to the v2. Add device information of v3 PMU with ACPI
> HID HISI0235.
>
> Signed-off-by: Junhao He <hejunhao3@huawei.com>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>