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Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, colinmitchell@google.com, chang.seok.bae@intel.com Subject: [PATCH v2 0/6] x86: Support for Intel Microcode Staging Feature Date: Thu, 20 Mar 2025 16:40:52 -0700 Message-ID: <20250320234104.8288-1-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi all, Here is a revision following up feedbacks from this posting [1]: * Instead of embedding staging logic directly into load_late_locked(), it was suggested [3] to place it within load_late_stop_cpus(). This change ensures that staging is treated as a preparatory step before CPUs are stopped. * Rather than introducing a separate .c file only for staging, the recommendation was to consolidate all staging-related code within intel.c [4]. * The previous implementation lacks clarity in explaining key aspects of the mailbox and staging handler. Improving documentation and readability in these areas was suggested as a necessary refinement [5,6], as I understood. * It was also requested to fold MSR definitions into their usage patches [7]. In addition to addressing these points, I’ve considered a unified staging state struct (patch 2), primarily to simplify the staging handler loop while also improving overall code organization. This series is based on the tip/master branch. You can also find it from this repo: git://github.com/intel-staging/microcode.git staging_v2 I suspect the maintainers could afford another look at least after the upcoming merge window. In the meantime, I would appreciate any additional feedback from those interested in this feature. The original cover letter, which provides some background on this feature enabling and its initial integration considerations, can be found in the previous postings [1,2]. The relevant specification has also been posted [8]. Thanks, Chang [1] Last posting: https://lore.kernel.org/lkml/20241211014213.3671-1-chang.seok.bae@intel.com/ [2] RFC: https://lore.kernel.org/lkml/20241001161042.465584-1-chang.seok.bae@intel.com/ [3] https://lore.kernel.org/lkml/20250218113634.GGZ7RwwkrrXADX0eRo@fat_crate.local/ [4] https://lore.kernel.org/lkml/20250226175642.GOZ79V2jWQTH5rbuXo@fat_crate.local/ [5] https://lore.kernel.org/lkml/fac46937-e0a5-42c1-96ee-65fec4e17551@intel.com/ [6] https://lore.kernel.org/lkml/1aee0888-b87b-443c-84fa-3bc000cbebcf@intel.com/ [7] https://lore.kernel.org/lkml/20250226171923.GMZ79NG_8wDtZ8vyWH@fat_crate.local/ [8] Staging Spec: https://cdrdv2.intel.com/v1/dl/getContent/782715 Chang S. Bae (6): x86/microcode: Introduce staging step to reduce late-loading time x86/microcode/intel: Define staging state struct x86/microcode/intel: Establish staging control logic x86/microcode/intel: Implement staging handler x86/microcode/intel: Support mailbox transfer x86/microcode/intel: Enable staging when available arch/x86/include/asm/msr-index.h | 9 + arch/x86/kernel/cpu/microcode/core.c | 11 + arch/x86/kernel/cpu/microcode/intel.c | 341 +++++++++++++++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 4 +- 4 files changed, 364 insertions(+), 1 deletion(-) base-commit: 758ea9705c51865858c612f591c6e6950dcafccf -- 2.45.2