[PATCH v3 34/35] perf vendor events: Update westmereep-dp events

Ian Rogers
2025-03-26T00:10:17Z

Update event topic moving other topic events to cache and virtual
memory.

Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/westmereep-sp/cache.json | 32 +++++++++++++++
.../arch/x86/westmereep-sp/other.json | 40 -------------------
.../x86/westmereep-sp/virtual-memory.json | 8 ++++
3 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
index 90cb367f5798..0cd571472dca 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json
@@ -119,6 +119,38 @@
"SampleAfterValue": "100000",
"UMask": "0x2"
},
+ {
+ "BriefDescription": "L1I instruction fetch stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.CYCLES_STALLED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "L1I instruction fetch hits",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.HITS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "L1I instruction fetch misses",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.MISSES",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "L1I Instruction fetches",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.READS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x3"
+ },
{
"BriefDescription": "All L2 data requests",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
index bcf5bcf637c0..c0cf8bae8074 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
@@ -15,46 +15,6 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
- {
- "BriefDescription": "L1I instruction fetch stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "L1I.CYCLES_STALLED",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "L1I instruction fetch hits",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "L1I.HITS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "L1I instruction fetch misses",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "L1I.MISSES",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "L1I Instruction fetches",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "L1I.READS",
- "SampleAfterValue": "2000000",
- "UMask": "0x3"
- },
- {
- "BriefDescription": "Large ITLB hit",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "LARGE_ITLB.HIT",
- "SampleAfterValue": "200000",
- "UMask": "0x1"
- },
{
"BriefDescription": "Loads that partially overlap an earlier store",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
index e7affdf7f41b..a1b22c82a9bf 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json
@@ -128,6 +128,14 @@
"SampleAfterValue": "200000",
"UMask": "0x20"
},
+ {
+ "BriefDescription": "Large ITLB hit",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x82",
+ "EventName": "LARGE_ITLB.HIT",
+ "SampleAfterValue": "200000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
--
2.49.0.395.g12beb8f557-goog