From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93D6D214226; Mon, 31 Mar 2025 14:35:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431755; cv=none; b=LSUq6kLmXAfjcytV0ALLRzMHYA+Pz9tsrYysg77+hwv3mQMJ5zDVCd9fuxuKlvgr7u28q8+6hFHtjaJQNf0dPl5+FSlt3qJm+Y2F10I2vwuUFsNdRADpO0dj2ruV5guAXCEGsQt154K4m/Ouuq6kmJ3VWh5mhBVoecI9crbpImI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743431755; c=relaxed/simple; bh=QQfSJ6URsGQRTmdqKZqvlDNd1JClNHUaKpoKWm2qpLo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TUTAfK2kZM7+EBo9hL7+lOH+bHhLXP2rPpVHamGDwhn8ggjQ0NmuHpGblaS3df6ecw6nMx8AK4g08BFGIiJW2kqKeo29yhZLI0yw5uHBzT4SD5zJAXZPi3KX/F7Sbck0y3EbZKbpjRhqSPvFHqTsHBMYVVru7BcTUKS+azRrFXM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n2l4EGC1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n2l4EGC1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0CC0C4CEE4; Mon, 31 Mar 2025 14:35:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743431755; bh=QQfSJ6URsGQRTmdqKZqvlDNd1JClNHUaKpoKWm2qpLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n2l4EGC1LKqFuVj6WbPr4CBb37qjr4H7OUQOCU1tgYbhjEBNivrorsf17kIJcn+Cg 7/GlIhTvpcRCJyya/x8dpWmAMadCVB0juVwq2I74ECrwwG4pli2CKmoyI5qDSZnNi6 NwMdNsbbVei2txhhdurpw2i/rH23uBXqzwt0eQCQq6EJ5p85mnhALDI44EvhvfzAqw KlgkviaOD1nM2LCgaizB+CcBE+R14hrueuFd0IRfkMv04A71iTVo+o5yFts1wtkebP mRr2YxkRB/sEP+U45tU2w24MzZRcfAAArbf5cb8NBl/TqPSNaDhLETR6bAIRkOVZfz 6qGAvStjj2E5A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Douglas Anderson , Dmitry Baryshkov , Trilok Soni , Catalin Marinas , Sasha Levin , will@kernel.org, mark.rutland@arm.com, oliver.upton@linux.dev, shameerali.kolothum.thodi@huawei.com, bwicaksono@nvidia.com, scott@os.amperecomputing.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.12 10/13] arm64: cputype: Add QCOM_CPU_PART_KRYO_3XX_GOLD Date: Mon, 31 Mar 2025 10:35:24 -0400 Message-Id: <20250331143528.1685794-10-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250331143528.1685794-1-sashal@kernel.org> References: <20250331143528.1685794-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.12.21 Content-Transfer-Encoding: 8bit From: Douglas Anderson [ Upstream commit 401c3333bb2396aa52e4121887a6f6a6e2f040bc ] Add a definition for the Qualcomm Kryo 300-series Gold cores. Reviewed-by: Dmitry Baryshkov Signed-off-by: Douglas Anderson Acked-by: Trilok Soni Link: https://lore.kernel.org/r/20241219131107.v3.1.I18e0288742871393228249a768e5d56ea65d93dc@changeid Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 488f8e7513495..c8058f91a5bd3 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -119,6 +119,7 @@ #define QCOM_CPU_PART_KRYO 0x200 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 +#define QCOM_CPU_PART_KRYO_3XX_GOLD 0x802 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 @@ -195,6 +196,7 @@ #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) +#define MIDR_QCOM_KRYO_3XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_GOLD) #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) -- 2.39.5