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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	asahi@lists.linux.dev
Cc: "Alyssa Rosenzweig" <alyssa@rosenzweig.io>,
	"Janne Grunau" <j@jannau.net>, "Hector Martin" <marcan@marcan.st>,
	"Sven Peter" <sven@svenpeter.dev>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Mark Kettenis" <mark.kettenis@xs4all.nl>
Subject: [PATCH v3 02/13] dt-bindings: pci: apple,pcie: Add t6020 compatible string
Date: Tue,  1 Apr 2025 10:17:02 +0100	[thread overview]
Message-ID: <20250401091713.2765724-3-maz@kernel.org> (raw)
In-Reply-To: <20250401091713.2765724-1-maz@kernel.org>

From: Alyssa Rosenzweig <alyssa@rosenzweig.io>

t6020 adds some register ranges compared to t8103, so requires
a new compatible as well as the new PHY registers.

Thanks to Mark and Rob for their helpful suggestions in updating
the binding.

Suggested-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Suggested-by: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tested-by: Janne Grunau <j@jannau.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
[maz: added PHY registers, constraints]
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 .../devicetree/bindings/pci/apple,pcie.yaml   | 33 +++++++++++++++----
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
index c8775f9cb0713..c0852be04f6de 100644
--- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
@@ -17,6 +17,10 @@ description: |
   implements its root ports.  But the ATU found on most DesignWare
   PCIe host bridges is absent.
 
+  On systems derived from T602x, the PHY registers are in a region
+  separate from the port registers. In that case, there is one PHY
+  register range per port register range.
+
   All root ports share a single ECAM space, but separate GPIOs are
   used to take the PCI devices on those ports out of reset.  Therefore
   the standard "reset-gpios" and "max-link-speed" properties appear on
@@ -30,16 +34,18 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - apple,t8103-pcie
-          - apple,t8112-pcie
-          - apple,t6000-pcie
-      - const: apple,pcie
+    oneOf:
+      - items:
+          - enum:
+              - apple,t8103-pcie
+              - apple,t8112-pcie
+              - apple,t6000-pcie
+          - const: apple,pcie
+      - const: apple,t6020-pcie
 
   reg:
     minItems: 3
-    maxItems: 6
+    maxItems: 10
 
   reg-names:
     minItems: 3
@@ -50,6 +56,10 @@ properties:
       - const: port1
       - const: port2
       - const: port3
+      - const: phy0
+      - const: phy1
+      - const: phy2
+      - const: phy3
 
   ranges:
     minItems: 2
@@ -98,6 +108,15 @@ allOf:
           maxItems: 5
         interrupts:
           maxItems: 3
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: apple,t6020-pcie
+    then:
+      properties:
+        reg-names:
+          minItems: 10
 
 examples:
   - |
-- 
2.39.2


  parent reply	other threads:[~2025-04-01  9:17 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-01  9:17 [PATCH v3 00/13] PCI: apple: Add support for t6020 Marc Zyngier
2025-04-01  9:17 ` [PATCH v3 01/13] PCI: apple: Set only available ports up Marc Zyngier
2025-04-13 16:57   ` Manivannan Sadhasivam
2025-04-13 20:00     ` Marc Zyngier
2025-04-14 10:13       ` Manivannan Sadhasivam
2025-04-01  9:17 ` Marc Zyngier [this message]
2025-04-01  9:40   ` [PATCH v3 02/13] dt-bindings: pci: apple,pcie: Add t6020 compatible string Mark Kettenis
2025-04-13 16:59   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 03/13] PCI: host-generic: Extract an ecam bridge creation helper from pci_host_common_probe() Marc Zyngier
2025-04-13 17:03   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 04/13] PCI: ecam: Allow cfg->priv to be pre-populated from the root port device Marc Zyngier
2025-04-13 17:04   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 05/13] PCI: apple: Move over to standalone probing Marc Zyngier
2025-04-13 17:06   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 06/13] PCI: apple: Dynamically allocate RID-to_SID bitmap Marc Zyngier
2025-04-13 17:07   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 07/13] PCI: apple: Move away from INTMSK{SET,CLR} for INTx and private interrupts Marc Zyngier
2025-04-13 17:09   ` Manivannan Sadhasivam
2025-04-22 17:41   ` Bjorn Helgaas
2025-04-22 17:49     ` Marc Zyngier
2025-04-01  9:17 ` [PATCH v3 08/13] PCI: apple: Fix missing OF node reference in apple_pcie_setup_port Marc Zyngier
2025-04-13 17:12   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 09/13] PCI: apple: Move port PHY registers to their own reg items Marc Zyngier
2025-04-13 17:16   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 10/13] PCI: apple: Drop poll for CORE_RC_PHYIF_STAT_REFCLK Marc Zyngier
2025-04-13 17:17   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 11/13] PCI: apple: Use gpiod_set_value_cansleep in probe flow Marc Zyngier
2025-04-13 17:17   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 12/13] PCI: apple: Abstract register offsets via a SoC-specific structure Marc Zyngier
2025-04-13 17:22   ` Manivannan Sadhasivam
2025-04-01  9:17 ` [PATCH v3 13/13] PCI: apple: Add T602x PCIe support Marc Zyngier
2025-04-13 17:24   ` Manivannan Sadhasivam
2025-04-19 14:59 ` [PATCH v3 00/13] PCI: apple: Add support for t6020 Manivannan Sadhasivam
2025-04-20  8:32   ` Marc Zyngier

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