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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c1845e66esm9181665f8f.18.2025.04.01.14.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 14:02:02 -0700 (PDT) Date: Tue, 1 Apr 2025 22:02:01 +0100 From: David Laight To: Jason Gunthorpe Cc: Xu Lu , Jessica Clarke , tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, alex@ghiti.fr, lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev Subject: Re: [External] Re: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform Message-ID: <20250401220201.1fa3ec76@pumpkin> In-Reply-To: <20250401154412.GI186258@ziepe.ca> References: <20250325144252.27403-1-luxu.kernel@bytedance.com> <9F043708-3BB6-46CF-BEC3-2636E9A388B7@jrtc27.com> <20250401154412.GI186258@ziepe.ca> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 1 Apr 2025 12:44:12 -0300 Jason Gunthorpe wrote: > On Wed, Mar 26, 2025 at 11:26:07AM +0800, Xu Lu wrote: > > Hi Jessica, > > > > > Is such a platform conformant to the specification? > > > > We have talked about this before [1]. I think the IOMMU spec does not > > mandate the implementation of 8-byte access functionality. The related > > sentences are listed below: > > > > "The 8-byte IOMMU registers are defined in such a way that software > > can perform two individual 4-byte accesses, or hardware can perform > > two independent 4-byte transactions resulting from an 8-byte access, > > to the high and low halves of the register, in that order, as long as > > the register semantics, with regard to side-effects, are respected > > between the two software accesses, or two hardware transactions, > > respectively." > > I think the commit message should explain an anyalsis that the code is > safe against the mentioned side effects due to ordering. > > And a comment should explain this: > > +#define riscv_iommu_writeq(iommu, addr, val) \ > + ((addr == RISCV_IOMMU_REG_IOHPMCYCLES) ? \ > + lo_hi_writeq_relaxed((val), (iommu)->reg + (addr)) : \ > + hi_lo_writeq_relaxed((val), (iommu)->reg + (addr))) > > As the naive reading of the above spec paragraph doesn't seem like > there are exceptions or why one register has to be the opposite order. > > Also missing () around addr It is also double-evaluating (addr). I hope there is a lock, interleaved accesses from multiple cpu may not work. David > > Jason >