From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <nifan.cxl@gmail.com>,
<dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<dan.j.williams@intel.com>, <bhelgaas@google.com>,
<mahesh@linux.ibm.com>, <ira.weiny@intel.com>, <oohall@gmail.com>,
<Benjamin.Cheatham@amd.com>, <rrichter@amd.com>,
<nathan.fontenot@amd.com>,
<Smita.KoralahalliChannabasappa@amd.com>, <lukas@wunner.de>,
<ming.li@zohomail.com>, <PradeepVineshReddy.Kodamati@amd.com>
Subject: Re: [PATCH v8 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions
Date: Thu, 17 Apr 2025 18:22:12 +0100 [thread overview]
Message-ID: <20250417182212.000078d2@huawei.com> (raw)
In-Reply-To: <20250327014717.2988633-15-terry.bowman@amd.com>
On Wed, 26 Mar 2025 20:47:15 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> The cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() functions
> are unnecessary helper function and only used for Endpoints. Remove these
> functions because they are not necessary and do not align with a common
> handling API for all CXL devices' errors.
Having done this, what does the double underscore in the naming denote?
I assume original intent was perhaps that only the wrappers should
ever be called. If that's not the case after this change maybe get
rid of the __ prefix?
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> ---
> drivers/cxl/core/pci.c | 17 ++++-------------
> 1 file changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index f2139b382839..a67925dfdbe1 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -670,11 +670,6 @@ static void __cxl_handle_cor_ras(struct device *cxl_dev, struct device *pcie_dev
> trace_cxl_aer_correctable_error(cxl_dev, pcie_dev, serial, status);
> }
>
> -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, NULL, cxlds->serial, cxlds->regs.ras);
Previously second parameter was NULL. After this change you pass &pdev->dev.
That makes it look at least like there is a functional change here.
If this doesn't matter perhaps you should explain why in the description.
> -}
> -
> /* CXL spec rev3.0 8.2.4.16.1 */
> static void header_log_copy(void __iomem *ras_base, u32 *log)
> {
> @@ -732,14 +727,8 @@ static pci_ers_result_t __cxl_handle_ras(struct device *cxl_dev, struct device *
> return PCI_ERS_RESULT_PANIC;
> }
>
> -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_ras(&cxlds->cxlmd->dev, NULL, cxlds->serial, cxlds->regs.ras);
> -}
> -
> #ifdef CONFIG_PCIEAER_CXL
>
> -
Unrelated change. I think this ifdef was added earlier in series so avoid
adding the bonus line wherever it came from...
> void cxl_port_cor_error_detected(struct device *cxl_dev,
> struct cxl_prot_error_info *err_info)
> {
> @@ -868,7 +857,8 @@ void cxl_cor_error_detected(struct device *dev, struct cxl_prot_error_info *err_
> if (cxlds->rcd)
> cxl_handle_rdport_errors(cxlds);
>
> - cxl_handle_endpoint_cor_ras(cxlds);
> + __cxl_handle_cor_ras(&cxlds->cxlmd->dev, &pdev->dev,
> + cxlds->serial, cxlds->regs.ras);
> }
> }
> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
> @@ -907,7 +897,8 @@ pci_ers_result_t cxl_error_detected(struct device *dev,
> * chance the situation is recoverable dump the status of the RAS
> * capability registers and bounce the active state of the memdev.
> */
> - ue = cxl_handle_endpoint_ras(cxlds);
> + ue = __cxl_handle_ras(&cxlds->cxlmd->dev, &pdev->dev,
> + cxlds->serial, cxlds->regs.ras);
> }
>
> if (ue)
next prev parent reply other threads:[~2025-04-17 17:22 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-27 1:47 [PATCH v8 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-03-27 1:47 ` [PATCH v8 01/16] PCI/CXL: Introduce PCIe helper function pcie_is_cxl() Terry Bowman
2025-03-27 15:11 ` Ira Weiny
2025-03-27 15:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 02/16] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-03-27 16:48 ` Bjorn Helgaas
2025-03-27 17:15 ` Bowman, Terry
2025-03-27 17:49 ` Bjorn Helgaas
2025-03-27 16:58 ` Ira Weiny
2025-03-27 17:17 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 03/16] CXL/AER: Introduce Kfifo for forwarding CXL errors Terry Bowman
2025-03-27 17:08 ` Bjorn Helgaas
2025-03-27 18:12 ` Bowman, Terry
2025-03-28 17:02 ` Bjorn Helgaas
2025-03-28 17:36 ` Bowman, Terry
2025-03-28 17:01 ` Ira Weiny
2025-04-07 13:43 ` Bowman, Terry
2025-04-04 16:53 ` Jonathan Cameron
2025-04-23 14:33 ` Jonathan Cameron
2025-04-23 15:04 ` Jonathan Cameron
2025-04-23 22:12 ` Gregory Price
2025-03-27 1:47 ` [PATCH v8 04/16] cxl/aer: AER service driver forwards CXL error to CXL driver Terry Bowman
2025-03-27 17:13 ` Bjorn Helgaas
2025-04-07 14:00 ` Bowman, Terry
2025-04-23 15:04 ` Jonathan Cameron
2025-04-24 14:17 ` Bowman, Terry
2025-04-25 13:18 ` Jonathan Cameron
2025-04-25 21:03 ` Bowman, Terry
2025-05-15 21:52 ` Bowman, Terry
2025-05-20 11:04 ` Jonathan Cameron
2025-05-20 13:21 ` Bowman, Terry
2025-05-21 18:34 ` Jonathan Cameron
2025-05-21 23:30 ` Bowman, Terry
2025-04-23 22:21 ` Gregory Price
2025-03-27 1:47 ` [PATCH v8 05/16] PCI/AER: CXL driver dequeues CXL error forwarded from AER service driver Terry Bowman
2025-03-27 4:43 ` kernel test robot
2025-04-23 16:28 ` Jonathan Cameron
2025-04-24 15:03 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 06/16] CXL/PCI: Introduce CXL uncorrectable protocol error 'recovery' Terry Bowman
2025-03-27 3:37 ` kernel test robot
2025-03-27 4:19 ` kernel test robot
2025-04-23 16:35 ` Jonathan Cameron
2025-04-24 14:22 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 07/16] cxl/pci: Move existing CXL RAS initialization to CXL's cxl_port driver Terry Bowman
2025-04-17 10:18 ` Jonathan Cameron
2025-04-24 14:25 ` Bowman, Terry
2025-05-12 14:47 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 08/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-03-27 1:47 ` [PATCH v8 09/16] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-03-27 1:47 ` [PATCH v8 10/16] cxl/pci: Add log message if RAS registers are not mapped Terry Bowman
2025-04-23 16:41 ` Jonathan Cameron
2025-04-24 14:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 11/16] cxl/pci: Unifi CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-04-23 16:44 ` Jonathan Cameron
2025-05-07 16:28 ` Shiju Jose
2025-05-07 18:30 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 12/16] cxl/pci: Assign CXL Port protocol error handlers Terry Bowman
2025-04-23 16:47 ` Jonathan Cameron
2025-03-27 1:47 ` [PATCH v8 13/16] cxl/pci: Assign CXL Endpoint " Terry Bowman
2025-03-27 19:46 ` kernel test robot
2025-04-23 16:49 ` Jonathan Cameron
2025-03-27 1:47 ` [PATCH v8 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-04-17 17:22 ` Jonathan Cameron [this message]
2025-03-27 1:47 ` [PATCH v8 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-04-04 17:05 ` Jonathan Cameron
2025-04-07 14:34 ` Bowman, Terry
2025-03-27 1:47 ` [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during CXL Port cleanup Terry Bowman
2025-03-28 1:18 ` kernel test robot
2025-04-04 17:04 ` Jonathan Cameron
2025-04-07 14:25 ` Bowman, Terry
2025-04-17 10:13 ` Jonathan Cameron
2025-04-24 16:37 ` Bowman, Terry
2025-03-27 17:16 ` [PATCH v8 00/16] Enable CXL PCIe port protocol error handling and logging Bjorn Helgaas
2025-03-27 22:04 ` Bowman, Terry
2025-05-06 23:06 ` Gregory Price
2025-05-07 18:28 ` Bowman, Terry
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