[PATCH 0/6] Add CMN PLL clock controller support for IPQ5018

[PATCH 0/6] Add CMN PLL clock controller support for IPQ5018

[George Moussalem via B4 Relay]

The CMN PLL block of IPQ5018 supplies output clocks for XO at 24 MHZ,
sleep at 32KHZ, and the ethernet block at 50MHZ.

This patch series extends the CMN PLL driver to support IPQ5018.
It also adds the SoC specific header file to export the CMN PLL
output clock specifiers for IPQ5018. The new table of output
clocks is added for the CMN PLL of IPQ5018, which is acquired
from the device according to the compatible.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
George Moussalem (6):
      dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
      clk: qcom: ipq5018: mark XO clock as critical
      clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
      dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018
      arm64: dts: ipq5018: Add CMN PLL node
      arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

 .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       | 11 +++-
 .../devicetree/bindings/mfd/qcom,tcsr.yaml         |  1 +
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |  3 +-
 .../dts/qcom/ipq5018-tplink-archer-ax55-v1.dts     |  3 +-
 arch/arm64/boot/dts/qcom/ipq5018.dtsi              | 40 +++++++++++-
 drivers/clk/qcom/gcc-ipq5018.c                     |  2 +-
 drivers/clk/qcom/ipq-cmn-pll.c                     | 72 ++++++++++++++++++----
 include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h   | 16 +++++
 8 files changed, 129 insertions(+), 19 deletions(-)
---
base-commit: 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
change-id: 20250501-ipq5018-cmn-pll-8e517de873f8
prerequisite-change-id: 20250411-qcom_ipq5424_cmnpll-960a8f597033:v2
prerequisite-patch-id: dc3949e10baf58f8c28d24bb3ffd347a78a1a2ee
prerequisite-patch-id: da645619780de3186a3cccf25beedd4fefab36df
prerequisite-patch-id: 4b5d81954f1f43d450a775bcabc1a18429933aaa
prerequisite-patch-id: 541f835fb279f83e6eb2405c531bd7da9aacf4bd

Best regards,
-- 
George Moussalem <george.moussalem@outlook.com>

[PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.

Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
first in IPQ5018. Hence, add optional phandle to TCSR register space
and offset to do so.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
 include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -24,12 +24,10 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq5018-cmn-pll
       - qcom,ipq5424-cmn-pll
       - qcom,ipq9574-cmn-pll
 
-  reg:
-    maxItems: 1
-
   clocks:
     items:
       - description: The reference clock. The supported clock rates include
@@ -50,6 +48,13 @@ properties:
   "#clock-cells":
     const: 1
 
+  qcom,cmn-pll-eth-enable:
+    description: Register in TCSR to enable CMN PLL to ethernet
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+        - description: phandle of TCSR syscon
+        - description: offset of TCSR register to enable CMN PLL to ethernet
+
 required:
   - compatible
   - reg
diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
new file mode 100644
index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ5018_CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ5018. */
+#define IPQ5018_XO_24MHZ_CLK			1
+#define IPQ5018_SLEEP_32KHZ_CLK			2
+#define IPQ5018_ETH_50MHZ_CLK			3
+#endif

-- 
2.49.0

[PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
flag to avoid the kernel trying to disable the XO clock (when parenting
it under the CMN PLL reference clock), else the kernel will panic and
the following message will appear in the kernel logs:

[    0.916515] ------------[ cut here ]------------
[    0.918890] gcc_xo_clk_src status stuck at 'on'
[    0.918944] WARNING: CPU: 0 PID: 8 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x114/0x124
[    0.927926] Modules linked in:
[    0.936945] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 6.6.74 #0
[    0.939982] Hardware name: Linksys MX2000 (DT)
[    0.946151] Workqueue: pm pm_runtime_work
[    0.950489] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    0.954566] pc : clk_branch_wait+0x114/0x124
[    0.961335] lr : clk_branch_wait+0x114/0x124
[    0.965849] sp : ffffffc08181bb50
[    0.970101] x29: ffffffc08181bb50 x28: 0000000000000000 x27: 61c8864680b583eb
[    0.973317] x26: ffffff801fec2168 x25: ffffff800000abc0 x24: 0000000000000002
[    0.980437] x23: ffffffc0809f6fd8 x22: 0000000000000000 x21: ffffffc08044193c
[    0.985276] loop: module loaded
[    0.987554] x20: 0000000000000000 x19: ffffffc081749278 x18: 000000000000007c
[    0.987573] x17: 0000000091706274 x16: 000000001985c4f7 x15: ffffffc0816bbdf0
[    0.987587] x14: 0000000000000174 x13: 000000000000007c x12: 00000000ffffffea
[    0.987601] x11: 00000000ffffefff x10: ffffffc081713df0 x9 : ffffffc0816bbd98
[    0.987615] x8 : 0000000000017fe8 x7 : c0000000ffffefff x6 : 0000000000057fa8
[    1.026268] x5 : 0000000000000fff x4 : 0000000000000000 x3 : ffffffc08181b950
[    1.033385] x2 : ffffffc0816bbd30 x1 : ffffffc0816bbd30 x0 : 0000000000000023
[    1.040507] Call trace:
[    1.047618]  clk_branch_wait+0x114/0x124
[    1.049875]  clk_branch2_disable+0x2c/0x3c
[    1.054043]  clk_core_disable+0x60/0xac
[    1.057948]  clk_core_disable+0x68/0xac
[    1.061681]  clk_disable+0x30/0x4c
[    1.065499]  pm_clk_suspend+0xd4/0xfc
[    1.068971]  pm_generic_runtime_suspend+0x2c/0x44
[    1.072705]  __rpm_callback+0x40/0x1bc
[    1.077392]  rpm_callback+0x6c/0x78
[    1.081038]  rpm_suspend+0xf0/0x5c0
[    1.084423]  pm_runtime_work+0xf0/0xfc
[    1.087895]  process_one_work+0x17c/0x2f8
[    1.091716]  worker_thread+0x2e8/0x4d4
[    1.095795]  kthread+0xdc/0xe0
[    1.099440]  ret_from_fork+0x10/0x20
[    1.102480] ---[ end trace 0000000000000000 ]---

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/clk/qcom/gcc-ipq5018.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..24eb4c40da63462077ee2e5714e838aa30ced2e3 100644
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -1371,7 +1371,7 @@ static struct clk_branch gcc_xo_clk = {
 				&gcc_xo_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
 		},
 	},

-- 
2.49.0

[PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
ethernet block. The CMN PLL to the ethernet block must be enabled first
by setting a specific register in the TCSR area set in the device tree.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/clk/qcom/ipq-cmn-pll.c | 72 +++++++++++++++++++++++++++++++++++-------
 1 file changed, 61 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
index b34d6faf67b8dd74402fabdb8dfe5ea52edd52f4..8e1faea1f980fd53f62b340aa31b6cf1b14f7923 100644
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
@@ -42,6 +42,7 @@
 #include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/mfd/syscon.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -50,6 +51,7 @@
 #include <linux/regmap.h>
 
 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
+#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
 
 #define CMN_PLL_REFCLK_SRC_SELECTION		0x28
@@ -72,6 +74,9 @@
 #define CMN_PLL_DIVIDER_CTRL			0x794
 #define CMN_PLL_DIVIDER_CTRL_FACTOR		GENMASK(9, 0)
 
+#define TCSR_CMN_PLL_ETH			0x4
+#define TCSR_CMN_PLL_ETH_ENABLE			BIT(0)
+
 /**
  * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
  * @id:	Clock specifier to be supplied
@@ -92,6 +97,7 @@ struct cmn_pll_fixed_output_clk {
 struct clk_cmn_pll {
 	struct regmap *regmap;
 	struct clk_hw hw;
+	struct regmap *tcsr;
 };
 
 #define CLK_PLL_OUTPUT(_id, _name, _rate) {		\
@@ -110,16 +116,10 @@ static const struct regmap_config ipq_cmn_pll_regmap_config = {
 	.fast_io = true,
 };
 
-static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
-	CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
-	CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
-	CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
-	CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
-	CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
-	CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
-	CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
-	CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
-	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
+static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = {
+	CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
+	CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
+	CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
 	{ /* Sentinel */ }
 };
 
@@ -136,6 +136,19 @@ static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
 	{ /* Sentinel */ }
 };
 
+static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
+	CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
+	CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
+	CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
+	CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
+	CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
+	CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
+	CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
+	CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
+	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
+	{ /* Sentinel */ }
+};
+
 /*
  * CMN PLL has the single parent clock, which supports the several
  * possible parent clock rates, each parent clock rate is reflected
@@ -380,11 +393,47 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
 	return ret;
 }
 
+static inline int ipq_cmn_pll_eth_enable(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	unsigned int cmn_pll_offset;
+	struct regmap *tcsr;
+	int ret;
+
+	tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,cmn-pll-eth-enable",
+						    1, &cmn_pll_offset);
+	if (IS_ERR(tcsr)) {
+		ret = PTR_ERR(tcsr);
+		/*
+		 * continue if -ENODEV is returned as not all IPQ SoCs
+		 * need to enable CMN PLL. If it's another error, return it.
+		 */
+		if (ret == -ENODEV)
+			tcsr = NULL;
+		else
+			return ret;
+	}
+
+	if (tcsr) {
+		ret = regmap_update_bits(tcsr, cmn_pll_offset + TCSR_CMN_PLL_ETH,
+					 TCSR_CMN_PLL_ETH_ENABLE, TCSR_CMN_PLL_ETH_ENABLE);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	int ret;
 
+	ret = ipq_cmn_pll_eth_enable(pdev);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Fail to enable CMN PLL to ethernet");
+
 	ret = devm_pm_runtime_enable(dev);
 	if (ret)
 		return ret;
@@ -439,8 +488,9 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = {
 };
 
 static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
-	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
+	{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
 	{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
+	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);

-- 
2.49.0

[PATCH 4/6] dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Document the qcom,tcsr-ipq5018 compatible.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index 7e7225aadae3285f59ec303294cf1515772a629b..14ae3f00ef7e00e607bba93f49f03bb244253b0e 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -41,6 +41,7 @@ properties:
           - qcom,sm8450-tcsr
           - qcom,tcsr-apq8064
           - qcom,tcsr-apq8084
+          - qcom,tcsr-ipq5018
           - qcom,tcsr-ipq5332
           - qcom,tcsr-ipq5424
           - qcom,tcsr-ipq6018

-- 
2.49.0

[PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5018 devices.

The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 39 +++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 8914f2ef0bc47fda243b19174f77ce73fc10757d..78368600ba44825b38f737a6d7837a80dc32efb6 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -2,12 +2,13 @@
 /*
  * IPQ5018 SoC device tree source
  *
- * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
 
 / {
@@ -16,6 +17,14 @@ / {
 	#size-cells = <2>;
 
 	clocks {
+		ref_96mhz_clk: ref-96mhz-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&xo_clk>;
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+		};
+
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -25,6 +34,12 @@ xo_board_clk: xo-board-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
+
+		xo_clk: xo-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+		};
 	};
 
 	cpus {
@@ -147,6 +162,21 @@ usbphy0: phy@5b000 {
 			status = "disabled";
 		};
 
+		cmn_pll: clock-controller@9b000 {
+			compatible = "qcom,ipq5018-cmn-pll";
+			reg = <0 0x0009b000 0 0x800>;
+			clocks = <&ref_96mhz_clk>,
+				 <&gcc GCC_CMN_BLK_AHB_CLK>,
+				 <&gcc GCC_CMN_BLK_SYS_CLK>;
+			clock-names = "ref",
+				      "ahb",
+				      "sys";
+			#clock-cells = <1>;
+			assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
+			assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
+			qcom,cmn-pll-eth-enable = <&tcsr 0x105c0>;
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5018-tlmm";
 			reg = <0x01000000 0x300000>;
@@ -187,6 +217,11 @@ tcsr_mutex: hwlock@1905000 {
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-ipq5018", "syscon";
+			reg = <0x01937000 0x21000>;
+		};
+
 		sdhc_1: mmc@7804000 {
 			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x7804000 0x1000>;

-- 
2.49.0

[PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
to the analog block routing channel.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts             | 3 ++-
 arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++-
 arch/arm64/boot/dts/qcom/ipq5018.dtsi                      | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..abb629678c023a2eb387ebf229f6dd1c30133b19 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -80,5 +80,6 @@ &usbphy0 {
 };
 
 &xo_board_clk {
-	clock-frequency = <24000000>;
+	clock-div = <4>;
+	clock-mult = <1>;
 };
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
@@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
 };
 
 &xo_board_clk {
-	clock-frequency = <24000000>;
+	clock-div = <4>;
+	clock-mult = <1>;
 };
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 78368600ba44825b38f737a6d7837a80dc32efb6..7e40f80e4795de25d55b5a19c1beb98e5abcdef3 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -31,7 +31,8 @@ sleep_clk: sleep-clk {
 		};
 
 		xo_board_clk: xo-board-clk {
-			compatible = "fixed-clock";
+			compatible = "fixed-factor-clock";
+			clocks = <&ref_96mhz_clk>;
 			#clock-cells = <0>;
 		};
 

-- 
2.49.0

Re: [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical

[Konrad Dybcio]

On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
> flag to avoid the kernel trying to disable the XO clock (when parenting
> it under the CMN PLL reference clock), else the kernel will panic and
> the following message will appear in the kernel logs:

Remove the struct definition for this clock (and the assignment in
blah_blah_clks[]) and replace it with:

qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */

Konrad

Re: [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support

[Konrad Dybcio]

On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
> ethernet block. The CMN PLL to the ethernet block must be enabled first
> by setting a specific register in the TCSR area set in the device tree.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---

[...]

> +static inline int ipq_cmn_pll_eth_enable(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	unsigned int cmn_pll_offset;
> +	struct regmap *tcsr;
> +	int ret;
> +
> +	tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,cmn-pll-eth-enable",
> +						    1, &cmn_pll_offset);

So we have syscon_regmap_lookup_by_phandle_args() and
syscon_regmap_lookup_by_phandle_optional(), but we could also
use a syscon_regmap_lookup_by_phandle_args_optional() - could
you add that in drivers/mfd/syscon.c?

> +	if (IS_ERR(tcsr)) {
> +		ret = PTR_ERR(tcsr);
> +		/*
> +		 * continue if -ENODEV is returned as not all IPQ SoCs
> +		 * need to enable CMN PLL. If it's another error, return it.
> +		 */
> +		if (ret == -ENODEV)
> +			tcsr = NULL;
> +		else
> +			return ret;
> +	}
> +
> +	if (tcsr) {
> +		ret = regmap_update_bits(tcsr, cmn_pll_offset + TCSR_CMN_PLL_ETH,

I think it's better to just pass the exact register that we need,
instead of some loosely defined subregion - especially given the
structure likely will change across platforms

> +					 TCSR_CMN_PLL_ETH_ENABLE, TCSR_CMN_PLL_ETH_ENABLE);

regmap_set_bits()

> +		if (ret)
> +			return ret;

You can initialize ret to 0 and return ret below, unconditionally

> +	}
> +
> +	return 0;
> +}
> +
>  static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> +	ret = ipq_cmn_pll_eth_enable(pdev);
> +	if (ret)
> +		return dev_err_probe(dev, ret,
> +				     "Fail to enable CMN PLL to ethernet");

Fail*ed*

Konrad

Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[Konrad Dybcio]

On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
> clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
> to the analog block routing channel.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[Rob Herring (Arm)]

On Fri, 02 May 2025 14:15:43 +0400, George Moussalem wrote:
> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
> ethernet (50Mhz) clocks.
> 
> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
> first in IPQ5018. Hence, add optional phandle to TCSR register space
> and offset to do so.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>  include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>  2 files changed, 24 insertions(+), 3 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml:55:9: [warning] wrong indentation: expected 6 but found 8 (indentation)

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.example.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250502-ipq5018-cmn-pll-v1-1-27902c1c4071@outlook.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical

[George Moussalem]

On 5/2/25 14:29, Konrad Dybcio wrote:
> On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
>> flag to avoid the kernel trying to disable the XO clock (when parenting
>> it under the CMN PLL reference clock), else the kernel will panic and
>> the following message will appear in the kernel logs:
> 
> Remove the struct definition for this clock (and the assignment in
> blah_blah_clks[]) and replace it with:
> 
> qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */

understood, thanks for the quick turnaround!

> 
> Konrad

Best regards,
George

Re: [PATCH 3/6] clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support

[George Moussalem]

On 5/2/25 14:38, Konrad Dybcio wrote:
> On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
>> ethernet block. The CMN PLL to the ethernet block must be enabled first
>> by setting a specific register in the TCSR area set in the device tree.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
> 
> [...]
> 
>> +static inline int ipq_cmn_pll_eth_enable(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	unsigned int cmn_pll_offset;
>> +	struct regmap *tcsr;
>> +	int ret;
>> +
>> +	tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,cmn-pll-eth-enable",
>> +						    1, &cmn_pll_offset);
> 
> So we have syscon_regmap_lookup_by_phandle_args() and
> syscon_regmap_lookup_by_phandle_optional(), but we could also
> use a syscon_regmap_lookup_by_phandle_args_optional() - could
> you add that in drivers/mfd/syscon.c?

Yeah, sounds like a good plan. This was basically doing the same but it 
would be better to add it to the syscon driver.

> 
>> +	if (IS_ERR(tcsr)) {
>> +		ret = PTR_ERR(tcsr);
>> +		/*
>> +		 * continue if -ENODEV is returned as not all IPQ SoCs
>> +		 * need to enable CMN PLL. If it's another error, return it.
>> +		 */
>> +		if (ret == -ENODEV)
>> +			tcsr = NULL;
>> +		else
>> +			return ret;
>> +	}
>> +
>> +	if (tcsr) {
>> +		ret = regmap_update_bits(tcsr, cmn_pll_offset + TCSR_CMN_PLL_ETH,
> 
> I think it's better to just pass the exact register that we need,
> instead of some loosely defined subregion - especially given the
> structure likely will change across platforms

Will do.

> 
>> +					 TCSR_CMN_PLL_ETH_ENABLE, TCSR_CMN_PLL_ETH_ENABLE);
> 
> regmap_set_bits()

Will do.

> 
>> +		if (ret)
>> +			return ret;
> 
> You can initialize ret to 0 and return ret below, unconditionally
> 
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
>>   {
>>   	struct device *dev = &pdev->dev;
>>   	int ret;
>>   
>> +	ret = ipq_cmn_pll_eth_enable(pdev);
>> +	if (ret)
>> +		return dev_err_probe(dev, ret,
>> +				     "Fail to enable CMN PLL to ethernet");
> 
> Fail*ed*

Will fix the spelling.

> 
> Konrad

Thanks,
George

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[Rob Herring]

On Fri, May 02, 2025 at 02:15:43PM +0400, George Moussalem wrote:
> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
> ethernet (50Mhz) clocks.
> 
> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
> first in IPQ5018. Hence, add optional phandle to TCSR register space
> and offset to do so.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>  include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>  2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> @@ -24,12 +24,10 @@ description:
>  properties:
>    compatible:
>      enum:
> +      - qcom,ipq5018-cmn-pll
>        - qcom,ipq5424-cmn-pll
>        - qcom,ipq9574-cmn-pll
>  
> -  reg:
> -    maxItems: 1
> -
>    clocks:
>      items:
>        - description: The reference clock. The supported clock rates include
> @@ -50,6 +48,13 @@ properties:
>    "#clock-cells":
>      const: 1
>  
> +  qcom,cmn-pll-eth-enable:
> +    description: Register in TCSR to enable CMN PLL to ethernet
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +        - description: phandle of TCSR syscon
> +        - description: offset of TCSR register to enable CMN PLL to ethernet

items:
  - items:
      - description: phandle of TCSR syscon
      - description: offset of TCSR register to enable CMN PLL to ethernet

Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[Dmitry Baryshkov]

On Fri, May 02, 2025 at 02:15:48PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
> clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
> to the analog block routing channel.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts             | 3 ++-
>  arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++-
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi                      | 3 ++-
>  3 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..abb629678c023a2eb387ebf229f6dd1c30133b19 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> @@ -80,5 +80,6 @@ &usbphy0 {
>  };
>  
>  &xo_board_clk {
> -	clock-frequency = <24000000>;
> +	clock-div = <4>;
> +	clock-mult = <1>;
>  };
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>  };
>  
>  &xo_board_clk {
> -	clock-frequency = <24000000>;
> +	clock-div = <4>;
> +	clock-mult = <1>;
>  };

Is the divider a part of the SoC? If so, please move these values to the SoC dtsi file.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 78368600ba44825b38f737a6d7837a80dc32efb6..7e40f80e4795de25d55b5a19c1beb98e5abcdef3 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -31,7 +31,8 @@ sleep_clk: sleep-clk {
>  		};
>  
>  		xo_board_clk: xo-board-clk {
> -			compatible = "fixed-clock";
> +			compatible = "fixed-factor-clock";
> +			clocks = <&ref_96mhz_clk>;
>  			#clock-cells = <0>;
>  		};
>  
> 
> -- 
> 2.49.0
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[George Moussalem]

On 5/2/25 18:45, Dmitry Baryshkov wrote:
> On Fri, May 02, 2025 at 02:15:48PM +0400, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
>> clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
>> to the analog block routing channel.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts             | 3 ++-
>>   arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++-
>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi                      | 3 ++-
>>   3 files changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..abb629678c023a2eb387ebf229f6dd1c30133b19 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> @@ -80,5 +80,6 @@ &usbphy0 {
>>   };
>>   
>>   &xo_board_clk {
>> -	clock-frequency = <24000000>;
>> +	clock-div = <4>;
>> +	clock-mult = <1>;
>>   };
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>> index 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>>   };
>>   
>>   &xo_board_clk {
>> -	clock-frequency = <24000000>;
>> +	clock-div = <4>;
>> +	clock-mult = <1>;
>>   };
> 
> Is the divider a part of the SoC? If so, please move these values to the SoC dtsi file.

my 'best guess' is that the ref clk for ipq5018 is always 96MHZ and the 
XO board clk is 24MHZ, so it should be safe to move it to the dtsi, but 
this is purely based on the 5 different board types I have.

@Luo Jie: can you confirm the above?

> 
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 78368600ba44825b38f737a6d7837a80dc32efb6..7e40f80e4795de25d55b5a19c1beb98e5abcdef3 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -31,7 +31,8 @@ sleep_clk: sleep-clk {
>>   		};
>>   
>>   		xo_board_clk: xo-board-clk {
>> -			compatible = "fixed-clock";
>> +			compatible = "fixed-factor-clock";
>> +			clocks = <&ref_96mhz_clk>;
>>   			#clock-cells = <0>;
>>   		};
>>   
>>
>> -- 
>> 2.49.0
>>
>>
> 

Thanks,
George

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[George Moussalem]

On 5/2/25 18:17, Rob Herring wrote:
> On Fri, May 02, 2025 at 02:15:43PM +0400, George Moussalem wrote:
>> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
>> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
>> ethernet (50Mhz) clocks.
>>
>> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
>> first in IPQ5018. Hence, add optional phandle to TCSR register space
>> and offset to do so.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>>   .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>>   include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>>   2 files changed, 24 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> @@ -24,12 +24,10 @@ description:
>>   properties:
>>     compatible:
>>       enum:
>> +      - qcom,ipq5018-cmn-pll
>>         - qcom,ipq5424-cmn-pll
>>         - qcom,ipq9574-cmn-pll
>>   
>> -  reg:
>> -    maxItems: 1
>> -
>>     clocks:
>>       items:
>>         - description: The reference clock. The supported clock rates include
>> @@ -50,6 +48,13 @@ properties:
>>     "#clock-cells":
>>       const: 1
>>   
>> +  qcom,cmn-pll-eth-enable:
>> +    description: Register in TCSR to enable CMN PLL to ethernet
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +        - description: phandle of TCSR syscon
>> +        - description: offset of TCSR register to enable CMN PLL to ethernet
> 
> items:
>    - items:
>        - description: phandle of TCSR syscon
>        - description: offset of TCSR register to enable CMN PLL to ethernet
> 
Fixed in next version, and validated by make dt_binding_check 
DT_SCHEMA_FILES=qcom,ipq9574-cmn-pll.yaml

Thanks,
George

Re: [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018

[Rob Herring (Arm)]

On Fri, 02 May 2025 14:15:42 +0400, George Moussalem wrote:
> The CMN PLL block of IPQ5018 supplies output clocks for XO at 24 MHZ,
> sleep at 32KHZ, and the ethernet block at 50MHZ.
> 
> This patch series extends the CMN PLL driver to support IPQ5018.
> It also adds the SoC specific header file to export the CMN PLL
> output clock specifiers for IPQ5018. The new table of output
> clocks is added for the CMN PLL of IPQ5018, which is acquired
> from the device according to the compatible.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
> George Moussalem (6):
>       dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
>       clk: qcom: ipq5018: mark XO clock as critical
>       clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
>       dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018
>       arm64: dts: ipq5018: Add CMN PLL node
>       arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
> 
>  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       | 11 +++-
>  .../devicetree/bindings/mfd/qcom,tcsr.yaml         |  1 +
>  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |  3 +-
>  .../dts/qcom/ipq5018-tplink-archer-ax55-v1.dts     |  3 +-
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi              | 40 +++++++++++-
>  drivers/clk/qcom/gcc-ipq5018.c                     |  2 +-
>  drivers/clk/qcom/ipq-cmn-pll.c                     | 72 ++++++++++++++++++----
>  include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h   | 16 +++++
>  8 files changed, 129 insertions(+), 19 deletions(-)
> ---
> base-commit: 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
> change-id: 20250501-ipq5018-cmn-pll-8e517de873f8
> prerequisite-change-id: 20250411-qcom_ipq5424_cmnpll-960a8f597033:v2
> prerequisite-patch-id: dc3949e10baf58f8c28d24bb3ffd347a78a1a2ee
> prerequisite-patch-id: da645619780de3186a3cccf25beedd4fefab36df
> prerequisite-patch-id: 4b5d81954f1f43d450a775bcabc1a18429933aaa
> prerequisite-patch-id: 541f835fb279f83e6eb2405c531bd7da9aacf4bd
> 
> Best regards,
> --
> George Moussalem <george.moussalem@outlook.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
 Deps: looking for dependencies matching 4 patch-ids
 Deps: Applying prerequisite patch: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
 Deps: Applying prerequisite patch: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support
 Deps: Applying prerequisite patch: [PATCH v2 3/4] arm64: dts: ipq5424: Add CMN PLL node
 Deps: Applying prerequisite patch: [PATCH v2 4/4] arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com:

arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dtb: clock-controller@9b000 (qcom,ipq5424-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: clock-controller@9b000 (qcom,ipq5018-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: clock-controller@9b000 (qcom,ipq5018-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb: clock-controller@9b000 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[Jie Luo]

On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
> ethernet (50Mhz) clocks.
> 
> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
> first in IPQ5018. Hence, add optional phandle to TCSR register space
> and offset to do so.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>   .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>   include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>   2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> @@ -24,12 +24,10 @@ description:
>   properties:
>     compatible:
>       enum:
> +      - qcom,ipq5018-cmn-pll
>         - qcom,ipq5424-cmn-pll
>         - qcom,ipq9574-cmn-pll
>   
> -  reg:
> -    maxItems: 1
> -

The property 'reg' should not be removed.

>     clocks:
>       items:
>         - description: The reference clock. The supported clock rates include
> @@ -50,6 +48,13 @@ properties:
>     "#clock-cells":
>       const: 1
>   
> +  qcom,cmn-pll-eth-enable:
> +    description: Register in TCSR to enable CMN PLL to ethernet
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +        - description: phandle of TCSR syscon
> +        - description: offset of TCSR register to enable CMN PLL to ethernet
> +

This TCSR should not be a part of CMN PLL, it is the LDO controller for
the internal GEPHY in IPQ5018 SoC, which can be moved to a part of GEPHY
device.

>   required:
>     - compatible
>     - reg
> diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
> +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
> +
> +/* CMN PLL core clock. */
> +#define IPQ5018_CMN_PLL_CLK			0
> +
> +/* The output clocks from CMN PLL of IPQ5018. */
> +#define IPQ5018_XO_24MHZ_CLK			1
> +#define IPQ5018_SLEEP_32KHZ_CLK			2
> +#define IPQ5018_ETH_50MHZ_CLK			3
> +#endif
> 

Re: [PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node

[Jie Luo]

On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem<george.moussalem@outlook.com>
> 
> Add CMN PLL node for enabling output clocks to the networking
> hardware blocks on IPQ5018 devices.
> 
> The reference clock of CMN PLL is routed from XO to the CMN PLL
> through the internal WiFi block.
> .XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.

The clock tree: .XO (48 MHZ)-->WiFi (multiplier/divider)--> 96 MHZ
to CMN PLL.

Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[Jie Luo]

On 5/2/2025 11:53 PM, George Moussalem wrote:
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55- 
>>> v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> index 
>>> 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>>>   };
>>>   &xo_board_clk {
>>> -    clock-frequency = <24000000>;
>>> +    clock-div = <4>;
>>> +    clock-mult = <1>;
>>>   };
>>
>> Is the divider a part of the SoC? If so, please move these values to 
>> the SoC dtsi file.
> 
> my 'best guess' is that the ref clk for ipq5018 is always 96MHZ and the 
> XO board clk is 24MHZ, so it should be safe to move it to the dtsi, but 
> this is purely based on the 5 different board types I have.
> 
> @Luo Jie: can you confirm the above?

The xo_board_clk is achieved by the bootstrap PINs, which should be
always 24 MHZ, we can move it to the RDP common DTSI if it is existed.

Re: [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical

[George Moussalem]

On 5/2/25 16:45, George Moussalem wrote:
> 
> 
> On 5/2/25 14:29, Konrad Dybcio wrote:
>> On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
>>> From: George Moussalem <george.moussalem@outlook.com>
>>>
>>> The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
>>> flag to avoid the kernel trying to disable the XO clock (when parenting
>>> it under the CMN PLL reference clock), else the kernel will panic and
>>> the following message will appear in the kernel logs:
>>
>> Remove the struct definition for this clock (and the assignment in
>> blah_blah_clks[]) and replace it with:
>>
>> qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */
> 
> understood, thanks for the quick turnaround!

Tested it, but then then the issue is still there. This time fixable by 
setting the CLK_IS_CRITICAL flag on gcc_xo_clk_src. I was looking at 
removing the struct for gcc_xo_clk_src too and use 
qcom_branch_set_clk_en, but there are clocks that refer to the 
gcc_xo_clk_src as their parent. I'm a bit hesitant to tinker with the 
GCC driver without access to the datasheet. The downstream driver 
actually has the CLK_IS_CRITICAL flag set too on gcc_xo_clk as initially 
proposed in this patch:

https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.5/drivers/clk/qcom/gcc-ipq5018.c#L1457

Are you okay with this suggested approach?

> 
>>
>> Konrad
> 
> Best regards,
> George

Best regards,
George

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[George Moussalem]

On 5/4/25 05:49, Jie Luo wrote:
> 
> 
> On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem <george.moussalem@outlook.com>
>>
>> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
>> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
>> ethernet (50Mhz) clocks.
>>
>> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
>> first in IPQ5018. Hence, add optional phandle to TCSR register space
>> and offset to do so.
>>
>> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
>> ---
>>    .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>>    include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>>    2 files changed, 24 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> @@ -24,12 +24,10 @@ description:
>>    properties:
>>      compatible:
>>        enum:
>> +      - qcom,ipq5018-cmn-pll
>>          - qcom,ipq5424-cmn-pll
>>          - qcom,ipq9574-cmn-pll
>>    
>> -  reg:
>> -    maxItems: 1
>> -
> 
> The property 'reg' should not be removed.

Moved it back, I unintentionally removed it. Thanks!

> 
>>      clocks:
>>        items:
>>          - description: The reference clock. The supported clock rates include
>> @@ -50,6 +48,13 @@ properties:
>>      "#clock-cells":
>>        const: 1
>>    
>> +  qcom,cmn-pll-eth-enable:
>> +    description: Register in TCSR to enable CMN PLL to ethernet
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +        - description: phandle of TCSR syscon
>> +        - description: offset of TCSR register to enable CMN PLL to ethernet
>> +
> 
> This TCSR should not be a part of CMN PLL, it is the LDO controller for
> the internal GEPHY in IPQ5018 SoC, which can be moved to a part of GEPHY
> device.

I'm preparing a patch for the ipq5018 GE PHY too so can move it there. 
Can you confirm the uniphy isn't dependent on this too? There are boards 
out there which don't use the GE PHY at all, so if the uniphy depends on 
it for SGMII/SGMII+, this approach wouldn't work.

> 
>>    required:
>>      - compatible
>>      - reg
>> diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
>> @@ -0,0 +1,16 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
>> +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
>> +
>> +/* CMN PLL core clock. */
>> +#define IPQ5018_CMN_PLL_CLK			0
>> +
>> +/* The output clocks from CMN PLL of IPQ5018. */
>> +#define IPQ5018_XO_24MHZ_CLK			1
>> +#define IPQ5018_SLEEP_32KHZ_CLK			2
>> +#define IPQ5018_ETH_50MHZ_CLK			3
>> +#endif
>>
> 

Best regards,
George

Re: [PATCH 5/6] arm64: dts: ipq5018: Add CMN PLL node

[George Moussalem]

On 5/4/25 05:53, Jie Luo wrote:
> 
> 
> On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
>> From: George Moussalem<george.moussalem@outlook.com>
>>
>> Add CMN PLL node for enabling output clocks to the networking
>> hardware blocks on IPQ5018 devices.
>>
>> The reference clock of CMN PLL is routed from XO to the CMN PLL
>> through the internal WiFi block.
>> .XO (96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.
> 
> The clock tree: .XO (48 MHZ)-->WiFi (multiplier/divider)--> 96 MHZ
> to CMN PLL.

Noted, thanks!

> 

Re: [PATCH 6/6] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock

[George Moussalem]

On 5/4/25 06:17, Jie Luo wrote:
> 
> 
> On 5/2/2025 11:53 PM, George Moussalem wrote:
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-
>>>> v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>>> index
>>>> 5bb021cb29cd39cb95035bfac1bdbc976439838b..7a25af57749c8e8c9a6a185437886b04b0d99e8e 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts
>>>> @@ -124,5 +124,6 @@ uart_pins: uart-pins-state {
>>>>    };
>>>>    &xo_board_clk {
>>>> -    clock-frequency = <24000000>;
>>>> +    clock-div = <4>;
>>>> +    clock-mult = <1>;
>>>>    };
>>>
>>> Is the divider a part of the SoC? If so, please move these values to
>>> the SoC dtsi file.
>>
>> my 'best guess' is that the ref clk for ipq5018 is always 96MHZ and the
>> XO board clk is 24MHZ, so it should be safe to move it to the dtsi, but
>> this is purely based on the 5 different board types I have.
>>
>> @Luo Jie: can you confirm the above?
> 
> The xo_board_clk is achieved by the bootstrap PINs, which should be
> always 24 MHZ, we can move it to the RDP common DTSI if it is existed.
> 
The RDP common DTSI doesn't exist. If the xo_board_clk is always 24MHZ 
and the ref clock always 96MHZ, can't we move it to the SoC DTSI? Else, 
I suggest we stick to setting the div/mult in the board DTS files.

Best regards,
George

Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

[Jie Luo]

On 5/4/2025 3:03 PM, George Moussalem wrote:
>>> +  qcom,cmn-pll-eth-enable:
>>> +    description: Register in TCSR to enable CMN PLL to ethernet
>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>> +    items:
>>> +        - description: phandle of TCSR syscon
>>> +        - description: offset of TCSR register to enable CMN PLL to 
>>> ethernet
>>> +
>>
>> This TCSR should not be a part of CMN PLL, it is the LDO controller for
>> the internal GEPHY in IPQ5018 SoC, which can be moved to a part of GEPHY
>> device.
> 
> I'm preparing a patch for the ipq5018 GE PHY too so can move it there. 
> Can you confirm the uniphy isn't dependent on this too? There are boards 
> out there which don't use the GE PHY at all, so if the uniphy depends on 
> it for SGMII/SGMII+, this approach wouldn't work.

This TCSR only impacts the GEPHY, has no effect on UNIPHY (PCS).

Re: [PATCH 2/6] clk: qcom: ipq5018: mark XO clock as critical

[Konrad Dybcio]

On 5/4/25 8:59 AM, George Moussalem wrote:
> 
> 
> On 5/2/25 16:45, George Moussalem wrote:
>>
>>
>> On 5/2/25 14:29, Konrad Dybcio wrote:
>>> On 5/2/25 12:15 PM, George Moussalem via B4 Relay wrote:
>>>> From: George Moussalem <george.moussalem@outlook.com>
>>>>
>>>> The XO clock must not be disabled, so let's add the CLK_IS_CRITICAL
>>>> flag to avoid the kernel trying to disable the XO clock (when parenting
>>>> it under the CMN PLL reference clock), else the kernel will panic and
>>>> the following message will appear in the kernel logs:
>>>
>>> Remove the struct definition for this clock (and the assignment in
>>> blah_blah_clks[]) and replace it with:
>>>
>>> qcom_branch_set_clk_en(regmap, 0x30030); /* GCC_XO_CLK */
>>
>> understood, thanks for the quick turnaround!
> 
> Tested it, but then then the issue is still there. This time fixable by setting the CLK_IS_CRITICAL flag on gcc_xo_clk_src. I was looking at removing the struct for gcc_xo_clk_src too and use qcom_branch_set_clk_en, but there are clocks that refer to the gcc_xo_clk_src as their parent. I'm a bit hesitant to tinker with the GCC driver without access to the datasheet. The downstream driver actually has the CLK_IS_CRITICAL flag set too on gcc_xo_clk as initially proposed in this patch:
> 
> https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.5/drivers/clk/qcom/gcc-ipq5018.c#L1457
> 
> Are you okay with this suggested approach?

Since turning off XO means the CPU (and nothing else on the soc for that
matter) clock will not tick, just unregister the RCG along with it

you can remove the .parent_hws (dont forget .num_parents along with it)
from the affected clocks, this is effectively cosmetic

Konrad

Re: [PATCH 4/6] dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018

[Rob Herring (Arm)]

On Fri, 02 May 2025 14:15:46 +0400, George Moussalem wrote:
> Document the qcom,tcsr-ipq5018 compatible.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>