From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3962233CC88; Mon, 5 May 2025 22:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746484651; cv=none; b=rZTJg+/c7rxHPtgggefUlmtHikOIgrx3G3yBaNCLdUzOIRWVyMn1m1HLWqGsyk6MEC6bbl1Klljl0d6vtW4jgCI7kNeZ23s2BDiWf5EYN47I/zW3ManV3AdRta2bs9J3N/jTKLCO0qLa6922e4U/V8FpPQUyJ5pyyp0hkRLjFw4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746484651; c=relaxed/simple; bh=eCKQVKgp/wQveZZfhkUBt62qIwVxM9ZGlVvD6XO/DGs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jNJ1YEy0z1vkHdq9eFMWHW+CQvEWim942Hb1q/waAt0xDLg1wRfkaxjR+fkikzDP2F8n4JBrL6/ge/GkeQUNfIUyhphXSSZNUbnTpeZ7fNncrOaXSEOVfGZFFit3ZI2DOvJ7WGY1Qu+JgiYMZ1uVmIefVV3GiokqJz47W2V1AgQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DvLAvFtT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DvLAvFtT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB28BC4CEEF; Mon, 5 May 2025 22:37:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746484651; bh=eCKQVKgp/wQveZZfhkUBt62qIwVxM9ZGlVvD6XO/DGs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DvLAvFtTJzO5oQ5ULZ4BTCNFtlsA1NERN+jGACjRNB2DyoMIV4iMTaGOI3g2+MZXS tWgRG0VIQaKyAdsS6a6N+jzY8p6M4v92aZr/M6JKvCGT3B43fVTigBsDYhNRGcbn04 LbnUi6AIx5+x1dx22OFDdiHUiiwfsrX2SEGIWa8Sba6OKX5lOpYx1bT6jOYaujsyel q7agwm4kF8UB6U1Ef9H5zjRxaWRsZd30AYhqLPW587TpKsRJNGgy6Q39xPTaT1jgEh F+EsrKVntMt1ulDW6VIpK2TPa438avL1XyoMNFXzA8LyR1PMYmznNBvQdV1g2T3O5U 7pPKkqLEgq/7Q== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ravi Bangoria , Peter Zijlstra , Namhyung Kim , Sasha Levin , mingo@redhat.com, acme@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH AUTOSEL 6.14 584/642] perf/amd/ibs: Fix ->config to sample period calculation for OP PMU Date: Mon, 5 May 2025 18:13:20 -0400 Message-Id: <20250505221419.2672473-584-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250505221419.2672473-1-sashal@kernel.org> References: <20250505221419.2672473-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.14.5 Content-Transfer-Encoding: 8bit From: Ravi Bangoria [ Upstream commit 598bdf4fefff5af4ce6d26d16f7b2a20808fc4cb ] Instead of using standard perf_event_attr->freq=0 and ->sample_period fields, IBS event in 'sample period mode' can also be opened by setting period value directly in perf_event_attr->config in a MaxCnt bit-field format. IBS OP MaxCnt bits are defined as: (high bits) IbsOpCtl[26:20] = IbsOpMaxCnt[26:20] (low bits) IbsOpCtl[15:0] = IbsOpMaxCnt[19:4] Perf event sample period can be derived from MaxCnt bits as: sample_period = (high bits) | ((low_bits) << 4); However, current code just masks MaxCnt bits and shifts all of them, including high bits, which is incorrect. Fix it. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-4-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 5d975c39701cb..58ad23205d59d 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -274,7 +274,7 @@ static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; struct perf_ibs *perf_ibs; - u64 max_cnt, config; + u64 config; int ret; perf_ibs = get_ibs_pmu(event->attr.type); @@ -321,10 +321,19 @@ static int perf_ibs_init(struct perf_event *event) if (!hwc->sample_period) hwc->sample_period = 0x10; } else { - max_cnt = config & perf_ibs->cnt_mask; + u64 period = 0; + + if (perf_ibs == &perf_ibs_op) { + period = (config & IBS_OP_MAX_CNT) << 4; + if (ibs_caps & IBS_CAPS_OPCNTEXT) + period |= config & IBS_OP_MAX_CNT_EXT_MASK; + } else { + period = (config & IBS_FETCH_MAX_CNT) << 4; + } + config &= ~perf_ibs->cnt_mask; - event->attr.sample_period = max_cnt << 4; - hwc->sample_period = event->attr.sample_period; + event->attr.sample_period = period; + hwc->sample_period = period; } if (!hwc->sample_period) -- 2.39.5