From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 340DF2F665B; Mon, 5 May 2025 23:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746487088; cv=none; b=j2eNEHPWX75q7raZxpp+5prfQDHQ7XhBJtrUzaloXV9ZPTi6cU9BKzZdnR4waeNwlEoudt0wC927EEC5oN2hP7TbkrtCYdbY69/beh8eLpY9ofXPEvNnRlMnDanG+4M3w5g4ubTuRybKs188FmKbjocFhQwP9Wz362tkovRh/7E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746487088; c=relaxed/simple; bh=aODPuwxiWJff9RzDxF69b5g2E2/R55ip7KWod8t+Nz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TlKBTzyVyl1mHrUIqm/cvFWPKeeTWceX0etTwQ+eObGSANXET2lDEFPV1gotyYR1gnKJCvFNyH+zcMyCRq8ecuJufY9kNQU0fX3djKvf2T4zKYf3VL7/nVk283hvCo1bUFaDcOSUswIKfPZfXDW85wouPWoa7wl1ZqEnzrXMMFc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=euremZ5M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="euremZ5M" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B74E0C4CEE4; Mon, 5 May 2025 23:18:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746487087; bh=aODPuwxiWJff9RzDxF69b5g2E2/R55ip7KWod8t+Nz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=euremZ5MWIXKRPnkn/JyHbvXrrQnu8jDzw0mAmIqwI12BRw0UQQqOPVXwQCIVNffp PV+Xj+pHlQdiRDaZ/5qhVDIXUjzq+2qk3Ma9QyvJRUOTmIx+z28tnRUZCaapQ8nou3 KEJpao+kRdjWgrZbY+7hjD82MouOrhCZRyz3rysNDVpbDDvNdoiSVLbxOSdcyU6miB cmWpyoK5pSCuah31TXb+D5PgSHsa1aywZbgOEus475LABEkNAOvGHWxEMFahGl9+IM +2cFjCb2a3+VRdOCK4RSrkk3wtOWF+aJTXnmMogl/TsNSTzdvVHoPemxlqUQqztu7L dxnVmiZ4i9RmQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ravi Bangoria , Peter Zijlstra , Namhyung Kim , Sasha Levin , mingo@redhat.com, acme@kernel.org, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH AUTOSEL 5.15 147/153] perf/amd/ibs: Fix perf_ibs_op.cnt_mask for CurCnt Date: Mon, 5 May 2025 19:13:14 -0400 Message-Id: <20250505231320.2695319-147-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250505231320.2695319-1-sashal@kernel.org> References: <20250505231320.2695319-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.15.181 Content-Transfer-Encoding: 8bit From: Ravi Bangoria [ Upstream commit 46dcf85566170d4528b842bf83ffc350d71771fa ] IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Acked-by: Namhyung Kim Link: https://lkml.kernel.org/r/20250115054438.1021-5-ravi.bangoria@amd.com Signed-off-by: Sasha Levin --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index b605e08f9a8ef..2b83056029942 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -803,7 +803,8 @@ static __init int perf_event_ibs_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |= (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } ret = perf_ibs_pmu_init(&perf_ibs_op, "ibs_op"); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 0e4efcde07831..cbfca9d2c419b 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -417,6 +417,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) -- 2.39.5