From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48EA6390E0C; Mon, 5 May 2025 23:16:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746486997; cv=none; b=LyqRha8tmQIQ3oltKucHATzNL7i5mfx5rfTjQr3aXx8bULgE1I2/cHhOnBWzZGobe6UfiU56RWRksMZl/oLmwqjJa06GXBednzEOI4ZlW2Lp6yakf74O/vaHDkvsqG7Da/nHLh8M5QA4EPaHTpUsq/7014gjC2QXJysrxsilP98= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746486997; c=relaxed/simple; bh=D2onoH0eioFutunK8t49CfkAwg7YCy58FHYrZHRgwp0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=heAvbJ1n+1ih3Z5X5lpU5CB3dZ7DMBG78IaeIHoffOAx+N0JJ5r0lCDbS7DaKYyTjooJqryUgsKNxwf8ko/JdvbijdBg7cprVTLwSFJTQVUkXzurY+Y1IzVe+eTt+gNrRovcaVWhuSBMQDl/HLZ6Z3iYs9kH5GUzRv/H1njwmQg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UxOBz7Ko; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UxOBz7Ko" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F234C4CEEF; Mon, 5 May 2025 23:16:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746486995; bh=D2onoH0eioFutunK8t49CfkAwg7YCy58FHYrZHRgwp0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UxOBz7KowbWH2ZRTO5Cq4sdXczlwdK2rhRKJgeB3+DtJKZquMdoBZF+3SBHqnZLGt 5/kzKtFIrwkGWC9ukKqWvonQGJChdEfMASoJM+dFWO2Gu8CiTrj72ab6CwYpBMhEx3 L0ZbxOHQSBxw6KOZqEwPPVlFIWhb2uHwZV5qoEXQGXebzUL7yWreDYJJnkjY6rKpfR dxvNYqmlIRPlEzD4Hn3DWIHWl74nDg4e7zIlvSKaPhqrbKg+9BL6dhn7PA+7120wx6 nBwo6VFav1JKwMB0AsUhOMJKawG//SrqEY27SZQZi8z8rrF40mdLO5+NlFWrDM+Jhi ZCZ8kmbceiZtg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paul Burton , Chao-ying Fu , Dragan Mladjenovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Serge Semin , Gregory CLEMENT , Daniel Lezcano , Thomas Bogendoerfer , Sasha Levin , tglx@linutronix.de, linux-mips@vger.kernel.org Subject: [PATCH AUTOSEL 5.15 097/153] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Mon, 5 May 2025 19:12:24 -0400 Message-Id: <20250505231320.2695319-97-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250505231320.2695319-1-sashal@kernel.org> References: <20250505231320.2695319-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.15.181 Content-Transfer-Encoding: 8bit From: Paul Burton [ Upstream commit 3128b0a2e0cf6e07aa78e5f8cf7dd9cd59dc8174 ] In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Tested-by: Serge Semin Tested-by: Gregory CLEMENT Acked-by: Daniel Lezcano Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index be4175f415ba5..1946691f6b322 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -119,6 +119,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -253,9 +256,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with -- 2.39.5