public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Jassi Brar" <jassisinghbrar@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
	Rahul Pathak <rpathak@ventanamicro.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Atish Patra <atish.patra@linux.dev>,
	Andrew Jones <ajones@ventanamicro.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Anup Patel <anup@brainfault.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order
Date: Sun, 11 May 2025 19:09:33 +0530	[thread overview]
Message-ID: <20250511133939.801777-18-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250511133939.801777-1-apatel@ventanamicro.com>

From: Sunil V L <sunilvl@ventanamicro.com>

Currently, the interrupt controller list is created without any order.
Create the list sorted with the GSI base of the interrupt controllers.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/acpi/riscv/irq.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
index cced960c2aef..95b4d7574ce3 100644
--- a/drivers/acpi/riscv/irq.c
+++ b/drivers/acpi/riscv/irq.c
@@ -115,7 +115,7 @@ struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi)
 static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr_idcs,
 					       u32 id, u32 type)
 {
-	struct riscv_ext_intc_list *ext_intc_element;
+	struct riscv_ext_intc_list *ext_intc_element, *node;
 
 	ext_intc_element = kzalloc(sizeof(*ext_intc_element), GFP_KERNEL);
 	if (!ext_intc_element)
@@ -125,7 +125,17 @@ static int __init riscv_acpi_register_ext_intc(u32 gsi_base, u32 nr_irqs, u32 nr
 	ext_intc_element->nr_irqs = nr_irqs;
 	ext_intc_element->nr_idcs = nr_idcs;
 	ext_intc_element->id = id;
-	list_add_tail(&ext_intc_element->list, &ext_intc_list);
+	if (list_empty(&ext_intc_list)) {
+		list_add(&ext_intc_element->list, &ext_intc_list);
+		return 0;
+	}
+
+	list_for_each_entry(node, &ext_intc_list, list) {
+		if (node->gsi_base < ext_intc_element->gsi_base)
+			break;
+	}
+
+	__list_add(&ext_intc_element->list, node->list.prev, &node->list);
 	return 0;
 }
 
-- 
2.43.0


  parent reply	other threads:[~2025-05-11 13:42 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-11 13:39 [PATCH v3 00/23] Linux SBI MPXY and RPMI drivers Anup Patel
2025-05-11 13:39 ` [PATCH v3 01/23] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-05-11 13:39 ` [PATCH v3 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-05-19 17:26   ` Rob Herring
2025-05-21  6:12     ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-05-11 13:39 ` [PATCH v3 04/23] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-05-11 13:39 ` [PATCH v3 05/23] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-05-11 13:39 ` [PATCH v3 06/23] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-05-11 13:39 ` [PATCH v3 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-05-12 18:54   ` Thomas Gleixner
2025-05-21  6:08     ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-05-12  7:07   ` Andy Shevchenko
2025-05-12  9:58     ` Rahul Pathak
2025-05-12 14:15       ` Andy Shevchenko
2025-05-22 13:14     ` Rahul Pathak
2025-05-23 16:35       ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 13/23] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-05-12  6:50   ` Andy Shevchenko
2025-05-21 11:37     ` Anup Patel
2025-05-21 14:11       ` Andy Shevchenko
2025-05-23 11:38         ` Anup Patel
2025-05-12 18:58   ` Thomas Gleixner
2025-05-21 11:37     ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-05-12  8:43   ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 15/23] ACPI: property: Add support for cells property Anup Patel
2025-05-12  7:16   ` Andy Shevchenko
2025-05-12  8:30     ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 16/23] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-05-11 13:39 ` Anup Patel [this message]
2025-05-11 13:39 ` [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-05-12  7:31   ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-05-11 13:39 ` [PATCH v3 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-05-12  7:28   ` Andy Shevchenko
2025-05-12  8:36     ` Sunil V L
2025-05-12  8:47       ` Andy Shevchenko
2025-05-12  8:57         ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 21/23] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-05-12  7:34   ` Andy Shevchenko
2025-05-12  8:42     ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-05-11 13:39 ` [PATCH v3 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250511133939.801777-18-apatel@ventanamicro.com \
    --to=apatel@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=anup@brainfault.org \
    --cc=atish.patra@linux.dev \
    --cc=brgl@bgdev.pl \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=jassisinghbrar@gmail.com \
    --cc=krzk+dt@kernel.org \
    --cc=lenb@kernel.org \
    --cc=leyfoon.tan@starfivetech.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=mika.westerberg@linux.intel.com \
    --cc=mturquette@baylibre.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=rafael@kernel.org \
    --cc=robh@kernel.org \
    --cc=rpathak@ventanamicro.com \
    --cc=samuel.holland@sifive.com \
    --cc=sboyd@kernel.org \
    --cc=sunilvl@ventanamicro.com \
    --cc=tglx@linutronix.de \
    --cc=ukleinek@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox