From: Anup Patel <apatel@ventanamicro.com>
To: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Uwe Kleine-König" <ukleinek@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
Rahul Pathak <rpathak@ventanamicro.com>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>,
Atish Patra <atish.patra@linux.dev>,
Andrew Jones <ajones@ventanamicro.com>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 04/23] RISC-V: Add defines for the SBI message proxy extension
Date: Sun, 11 May 2025 19:09:20 +0530 [thread overview]
Message-ID: <20250511133939.801777-5-apatel@ventanamicro.com> (raw)
In-Reply-To: <20250511133939.801777-1-apatel@ventanamicro.com>
Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/sbi.h | 60 ++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 4dd6aafb8468..d295c26a7c26 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -35,6 +35,7 @@ enum sbi_ext_id {
SBI_EXT_DBCN = 0x4442434E,
SBI_EXT_STA = 0x535441,
SBI_EXT_NACL = 0x4E41434C,
+ SBI_EXT_MPXY = 0x4D505859,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -402,6 +403,65 @@ enum sbi_ext_nacl_feature {
#define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
#define SBI_NACL_SHMEM_SRET_X_LAST 31
+enum sbi_ext_mpxy_fid {
+ SBI_EXT_MPXY_GET_SHMEM_SIZE,
+ SBI_EXT_MPXY_SET_SHMEM,
+ SBI_EXT_MPXY_GET_CHANNEL_IDS,
+ SBI_EXT_MPXY_READ_ATTRS,
+ SBI_EXT_MPXY_WRITE_ATTRS,
+ SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
+ SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
+ SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
+};
+
+enum sbi_mpxy_attribute_id {
+ /* Standard channel attributes managed by MPXY framework */
+ SBI_MPXY_ATTR_MSG_PROT_ID = 0x00000000,
+ SBI_MPXY_ATTR_MSG_PROT_VER = 0x00000001,
+ SBI_MPXY_ATTR_MSG_MAX_LEN = 0x00000002,
+ SBI_MPXY_ATTR_MSG_SEND_TIMEOUT = 0x00000003,
+ SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT = 0x00000004,
+ SBI_MPXY_ATTR_CHANNEL_CAPABILITY = 0x00000005,
+ SBI_MPXY_ATTR_SSE_EVENT_ID = 0x00000006,
+ SBI_MPXY_ATTR_MSI_CONTROL = 0x00000007,
+ SBI_MPXY_ATTR_MSI_ADDR_LO = 0x00000008,
+ SBI_MPXY_ATTR_MSI_ADDR_HI = 0x00000009,
+ SBI_MPXY_ATTR_MSI_DATA = 0x0000000A,
+ SBI_MPXY_ATTR_EVENTS_STATE_CONTROL = 0x0000000B,
+ SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
+ /*
+ * Message protocol specific attributes, managed by
+ * the message protocol specification.
+ */
+ SBI_MPXY_ATTR_MSGPROTO_ATTR_START = 0x80000000,
+ SBI_MPXY_ATTR_MSGPROTO_ATTR_END = 0xffffffff
+};
+
+/* Possible values of MSG_PROT_ID attribute */
+enum sbi_mpxy_msgproto_id {
+ SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
+};
+
+/** RPMI message protocol specific MPXY attributes */
+enum sbi_mpxy_rpmi_attribute_id {
+ SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
+ SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
+ SBI_MPXY_RPMI_ATTR_MAX_ID,
+};
+
+/* Encoding of MSG_PROT_VER attribute */
+#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver) (((__ver) >> 16) & 0xffff)
+#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver) ((__ver) & 0xffff)
+#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min) (((__maj) << 16) | (__min))
+
+/* Capabilities available through CHANNEL_CAPABILITY attribute */
+#define SBI_MPXY_CHAN_CAP_MSI BIT(0)
+#define SBI_MPXY_CHAN_CAP_SSE BIT(1)
+#define SBI_MPXY_CHAN_CAP_EVENTS_STATE BIT(2)
+#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP BIT(3)
+#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP BIT(4)
+#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS BIT(5)
+
/* SBI spec version fields */
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
--
2.43.0
next prev parent reply other threads:[~2025-05-11 13:40 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-11 13:39 [PATCH v3 00/23] Linux SBI MPXY and RPMI drivers Anup Patel
2025-05-11 13:39 ` [PATCH v3 01/23] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-05-11 13:39 ` [PATCH v3 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-05-19 17:26 ` Rob Herring
2025-05-21 6:12 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-05-11 13:39 ` Anup Patel [this message]
2025-05-11 13:39 ` [PATCH v3 05/23] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-05-11 13:39 ` [PATCH v3 06/23] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-05-11 13:39 ` [PATCH v3 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-05-12 18:54 ` Thomas Gleixner
2025-05-21 6:08 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-05-12 7:07 ` Andy Shevchenko
2025-05-12 9:58 ` Rahul Pathak
2025-05-12 14:15 ` Andy Shevchenko
2025-05-22 13:14 ` Rahul Pathak
2025-05-23 16:35 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-05-11 13:39 ` [PATCH v3 13/23] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-05-12 6:50 ` Andy Shevchenko
2025-05-21 11:37 ` Anup Patel
2025-05-21 14:11 ` Andy Shevchenko
2025-05-23 11:38 ` Anup Patel
2025-05-12 18:58 ` Thomas Gleixner
2025-05-21 11:37 ` Anup Patel
2025-05-11 13:39 ` [PATCH v3 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-05-12 8:43 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 15/23] ACPI: property: Add support for cells property Anup Patel
2025-05-12 7:16 ` Andy Shevchenko
2025-05-12 8:30 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 16/23] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-05-11 13:39 ` [PATCH v3 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order Anup Patel
2025-05-11 13:39 ` [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-05-12 7:31 ` Andy Shevchenko
2025-05-11 13:39 ` [PATCH v3 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-05-11 13:39 ` [PATCH v3 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-05-12 7:28 ` Andy Shevchenko
2025-05-12 8:36 ` Sunil V L
2025-05-12 8:47 ` Andy Shevchenko
2025-05-12 8:57 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 21/23] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-05-12 7:34 ` Andy Shevchenko
2025-05-12 8:42 ` Sunil V L
2025-05-11 13:39 ` [PATCH v3 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-05-11 13:39 ` [PATCH v3 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel
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