* [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port
@ 2025-03-24 2:09 Sandie Cao
2025-04-09 21:28 ` Conor Dooley
2025-05-15 21:08 ` Conor Dooley
0 siblings, 2 replies; 4+ messages in thread
From: Sandie Cao @ 2025-03-24 2:09 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv, devicetree,
linux-kernel, sandie.cao, Maud Spierings
Add usb_cdns3 and usb0_pins configuration to support super speed USB
device on the FML13V01 board.
Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
---
Changes in v2:
- Remove space to pass checkpatch.pl.
- Add usb0_pins and pass test on board.
.../jh7110-deepcomputing-fml13v01.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 8d9ce8b69a71..f2857d021d68 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -43,9 +43,28 @@ GPOEN_DISABLE,
slew-rate = <0>;
};
};
+
+ usb0_pins: usb0-0 {
+ vbus-pins {
+ pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
};
&usb0 {
dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins>;
status = "okay";
};
+
+&usb_cdns3 {
+ phys = <&usbphy0>, <&pciephy0>;
+ phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
base-commit: 38818f7c9c179351334b1faffc4d40bd28cc9c72
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port
2025-03-24 2:09 [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port Sandie Cao
@ 2025-04-09 21:28 ` Conor Dooley
2025-05-15 14:24 ` Emil Renner Berthing
2025-05-15 21:08 ` Conor Dooley
1 sibling, 1 reply; 4+ messages in thread
From: Conor Dooley @ 2025-04-09 21:28 UTC (permalink / raw)
To: Sandie Cao
Cc: Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv, devicetree,
linux-kernel, Maud Spierings
[-- Attachment #1: Type: text/plain, Size: 1574 bytes --]
On Mon, Mar 24, 2025 at 10:09:58AM +0800, Sandie Cao wrote:
> Add usb_cdns3 and usb0_pins configuration to support super speed USB
> device on the FML13V01 board.
>
> Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
> Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Emil, can I grab this one?
> ---
>
> Changes in v2:
> - Remove space to pass checkpatch.pl.
> - Add usb0_pins and pass test on board.
>
> .../jh7110-deepcomputing-fml13v01.dts | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> index 8d9ce8b69a71..f2857d021d68 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -43,9 +43,28 @@ GPOEN_DISABLE,
> slew-rate = <0>;
> };
> };
> +
> + usb0_pins: usb0-0 {
> + vbus-pins {
> + pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> };
>
> &usb0 {
> dr_mode = "host";
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb0_pins>;
> status = "okay";
> };
> +
> +&usb_cdns3 {
> + phys = <&usbphy0>, <&pciephy0>;
> + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> +};
>
> base-commit: 38818f7c9c179351334b1faffc4d40bd28cc9c72
> --
> 2.34.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port
2025-04-09 21:28 ` Conor Dooley
@ 2025-05-15 14:24 ` Emil Renner Berthing
0 siblings, 0 replies; 4+ messages in thread
From: Emil Renner Berthing @ 2025-05-15 14:24 UTC (permalink / raw)
To: Conor Dooley, Sandie Cao
Cc: Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv, devicetree,
linux-kernel, Maud Spierings
Conor Dooley wrote:
> On Mon, Mar 24, 2025 at 10:09:58AM +0800, Sandie Cao wrote:
> > Add usb_cdns3 and usb0_pins configuration to support super speed USB
> > device on the FML13V01 board.
> >
> > Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
> > Tested-by: Maud Spierings <maud_spierings@hotmail.com>
>
> Emil, can I grab this one?
Yes, please do.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> > ---
> >
> > Changes in v2:
> > - Remove space to pass checkpatch.pl.
> > - Add usb0_pins and pass test on board.
> >
> > .../jh7110-deepcomputing-fml13v01.dts | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > index 8d9ce8b69a71..f2857d021d68 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > @@ -43,9 +43,28 @@ GPOEN_DISABLE,
> > slew-rate = <0>;
> > };
> > };
> > +
> > + usb0_pins: usb0-0 {
> > + vbus-pins {
> > + pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-disable;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > + };
> > };
> >
> > &usb0 {
> > dr_mode = "host";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&usb0_pins>;
> > status = "okay";
> > };
> > +
> > +&usb_cdns3 {
> > + phys = <&usbphy0>, <&pciephy0>;
> > + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> > +};
> >
> > base-commit: 38818f7c9c179351334b1faffc4d40bd28cc9c72
> > --
> > 2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port
2025-03-24 2:09 [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port Sandie Cao
2025-04-09 21:28 ` Conor Dooley
@ 2025-05-15 21:08 ` Conor Dooley
1 sibling, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2025-05-15 21:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
E Shattow, Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Sandie Cao
Cc: Conor Dooley, linux-kernel, devicetree, linux-riscv,
Maud Spierings
From: Conor Dooley <conor.dooley@microchip.com>
On Mon, 24 Mar 2025 10:09:58 +0800, Sandie Cao wrote:
> Add usb_cdns3 and usb0_pins configuration to support super speed USB
> device on the FML13V01 board.
>
>
Applied to riscv-dt-for-next, thanks!
[1/1] riscv: dts: starfive: fml13v01: enable USB 3.0 port
https://git.kernel.org/conor/c/a2e7f6c48740
Thanks,
Conor.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2025-03-24 2:09 [PATCH v2 RESEND] riscv: dts: starfive: fml13v01: enable USB 3.0 port Sandie Cao
2025-04-09 21:28 ` Conor Dooley
2025-05-15 14:24 ` Emil Renner Berthing
2025-05-15 21:08 ` Conor Dooley
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