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Shutemov" Content-Type: text/plain; charset="UTF-8" From: Ard Biesheuvel This is a follow-up to the discussion at [0], broken out of that series so we can progress while the SEV changes are being reviewed and tested. The current implementation of pgtable_l5_enabled() is problematic because it has two implementations, and source files need to opt into the correct one if they contain code that might be called very early. Other related global pseudo-constants exist that assume different values based on the number of paging levels, and it is hard to reason about whether or not all memory mapping and page table code is guaranteed to observe consistent values of all of these at all times during the boot. Case in point: currently, KASAN needs to be disabled during alternatives patching because otherwise, it will reliably produce false positive reports due to such inconsistencies. This series drops the early variant entirely, and makes the existing late variant, which is based on cpu_feature_enabled(), work as expected in all cases by tweaking the CPU capability code so that it permits setting the 5-level paging capability from assembler before calling the C entrypoint of the core kernel. Runtime constants were considered for PGDIR_SHIFT and PTRS_PER_P4D but were found unsuitable as they do not support loadable modules, and so they are replaced with expressions based on pgtable_l5_enabled(). Earlier patching of alternatives based on CPU capabilities may be feasible, but whether or not this improves performance is TBD. In any case, doing so from the startup code is unlikely to be worth the added complexity. Build and boot tested using QEMU with LA57 emulation. Changes since v3: - Drop asm-offsets patch which has been merged already - Rebase onto tip/x86/core which now carries some related changes by Kirill - Avoid adding new instances of '#ifdef CONFIG_X86_5LEVEL' where possible, as it is going to be removed soon - Move cap override arrays straight to __ro_after_init - Drop KVM changes entirely - they were wrong and unnecessary - Drop the new "la57_hw" capability flag for now - we can always add it later if there is a need. Changes since v2: - Drop first patch which has been merged - Rename existing "la57" CPU flag to "la57_hw" and use "la57" to indicate that 5 level paging is being used - Move memset() out of identify_cpu() - Make set/clear cap override arrays ro_after_init - Split off asm-offsets update [0] https://lore.kernel.org/all/20250504095230.2932860-28-ardb+git@google.com/ Cc: Ingo Molnar Cc: Linus Torvalds Cc: Brian Gerst Cc: Kirill A. Shutemov Ard Biesheuvel (6): x86/cpu: Use a new feature flag for 5 level paging x86/cpu: Move CPU capability override arrays from BSS to __ro_after_init x86/cpu: Allow caps to be set arbitrarily early x86/boot: Set 5-level paging CPU cap before entering C code x86/boot: Drop the early variant of pgtable_l5_enabled() x86/boot: Drop 5-level paging related variables and early updates arch/x86/boot/compressed/misc.h | 6 ++-- arch/x86/boot/compressed/pgtable_64.c | 12 -------- arch/x86/boot/startup/map_kernel.c | 21 +------------ arch/x86/boot/startup/sme.c | 9 ------ arch/x86/include/asm/cpufeature.h | 12 ++++++-- arch/x86/include/asm/cpufeatures.h | 3 +- arch/x86/include/asm/page_64.h | 2 +- arch/x86/include/asm/pgtable_64_types.h | 31 ++++---------------- arch/x86/kernel/alternative.c | 12 -------- arch/x86/kernel/cpu/common.c | 26 ++-------------- arch/x86/kernel/head64.c | 11 ------- arch/x86/kernel/head_64.S | 13 ++++++++ arch/x86/mm/kasan_init_64.c | 3 -- drivers/iommu/amd/init.c | 4 +-- drivers/iommu/intel/svm.c | 4 +-- 15 files changed, 41 insertions(+), 128 deletions(-) base-commit: 4375decf50f74878e73c29c9dcd8af51dd3f7376 -- 2.49.0.1101.gccaa498523-goog