From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3D5A21D3E3; Mon, 19 May 2025 21:22:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747689743; cv=none; b=PX9IKjbYlQCAaODyWHSAm246lMko+etkecFbs+VwJzyHlcRSIZxRXrO7flbEnuwjAWngN3UBOYtHxrHHNQVml2YSfUQbyRkLoR+xfgD92prSwUAVIlZGJs3tHgAcxVliYiFpF3YHgD97HqiaUuiRzvOFNaNpM/1s2P94dBVIv18= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747689743; c=relaxed/simple; bh=NRQTrFJKsX97jTiZqIvoELGtndJGz3IEGk7s35ac0lQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H402GDLGiVTBQccXcyyd5Vsf/zNYRcUxFO4yQlI49maP4q3qmEcMNefRJGmrk4wtF7x0XdyQBoqEWLC41D8dooBo/Gc+Wgkq+cKi2+jHnw7XIhA6AuD/Su1w8kVnXT36W7HnG0NinhyB/lsewERk2/+87D46w8V8mbMjTLDQ0vE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MpSs7uas; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MpSs7uas" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C35CCC4CEE9; Mon, 19 May 2025 21:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747689743; bh=NRQTrFJKsX97jTiZqIvoELGtndJGz3IEGk7s35ac0lQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MpSs7uasCDqjD6chRV0+Q+Di0oetBwrycXrVw6nyj1u5U052FvExMST5iw+VmoJwa 0xpg2zlwpdmRj2FL5f/PCT0lZAT6ofniW/lha0vwyznX+F9g4ONvHICJcyj8whq4Mt NIudRmzk0+4ZIDrXVEcuWHQvq3V4pYd6iIxn/dzRBTkw9WnLD5rpoW9aIMGmwyyJ/v wS6ABUQxF5mvJBqP2YsECWYBpgO7iRdAj6IdvIquCxBV7+JiYFlcCieC6RvfRvfqAm g8ezbzTTb4jrZhSKRiK2zZ7SGU3XAxLBHIUPiDJOhwYzFc3tmwLt8iIvFb1x4P/bQa E8rh4i0Usldwg== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: Hal Feng , Vinod Koul , Sasha Levin , kishon@ti.com, linux-kernel@vger.kernel.org Subject: [PATCH AUTOSEL 6.12 09/18] phy: starfive: jh7110-usb: Fix USB 2.0 host occasional detection failure Date: Mon, 19 May 2025 17:21:58 -0400 Message-Id: <20250519212208.1986028-9-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250519212208.1986028-1-sashal@kernel.org> References: <20250519212208.1986028-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.12.29 Content-Transfer-Encoding: 8bit From: Hal Feng [ Upstream commit 3f097adb9b6c804636bcf8d01e0e7bc037bee0d3 ] JH7110 USB 2.0 host fails to detect USB 2.0 devices occasionally. With a long time of debugging and testing, we found that setting Rx clock gating control signal to normal power consumption mode can solve this problem. Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20250422101244.51686-1-hal.feng@starfivetech.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/starfive/phy-jh7110-usb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c index cb5454fbe2c8f..b505d89860b43 100644 --- a/drivers/phy/starfive/phy-jh7110-usb.c +++ b/drivers/phy/starfive/phy-jh7110-usb.c @@ -18,6 +18,8 @@ #include #define USB_125M_CLK_RATE 125000000 +#define USB_CLK_MODE_OFF 0x0 +#define USB_CLK_MODE_RX_NORMAL_PWR BIT(1) #define USB_LS_KEEPALIVE_OFF 0x4 #define USB_LS_KEEPALIVE_ENABLE BIT(4) @@ -78,6 +80,7 @@ static int jh7110_usb2_phy_init(struct phy *_phy) { struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); int ret; + unsigned int val; ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE); if (ret) @@ -87,6 +90,10 @@ static int jh7110_usb2_phy_init(struct phy *_phy) if (ret) return ret; + val = readl(phy->regs + USB_CLK_MODE_OFF); + val |= USB_CLK_MODE_RX_NORMAL_PWR; + writel(val, phy->regs + USB_CLK_MODE_OFF); + return 0; } -- 2.39.5