[PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Mikhail Paulyshka]

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an
error that causes RDSEED to always return 0xffffffff, while RDRAND
works correctly.

This patch masks the RDSEED cap for this CPU so that both
/proc/cpuinfo and direct CPUID read report RDSEED as unavailable.


v2:
  * Limit changes to AMD Cyan Skillfish
  * Replace the runtime RDSEED sanity check with a simple
    family/model/stepping match

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
---
 arch/x86/include/asm/msr-index.h       | 1 +
 arch/x86/kernel/cpu/rdrand.c           | 9 +++++++++
 tools/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 11 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e7d2f460fcc6..2333f4e7bc2f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -624,6 +624,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
diff --git a/arch/x86/kernel/cpu/rdrand.c b/arch/x86/kernel/cpu/rdrand.c
index eeac00d20926..c474d0a5c317 100644
--- a/arch/x86/kernel/cpu/rdrand.c
+++ b/arch/x86/kernel/cpu/rdrand.c
@@ -11,6 +11,7 @@
 #include <asm/processor.h>
 #include <asm/archrandom.h>
 #include <asm/sections.h>
+#include <asm/msr.h>
 
 /*
  * RDRAND has Built-In-Self-Test (BIST) that runs on every invocation.
@@ -47,4 +48,12 @@ void x86_init_rdrand(struct cpuinfo_x86 *c)
 		clear_cpu_cap(c, X86_FEATURE_RDSEED);
 		pr_emerg("RDRAND is not reliable on this platform; disabling.\n");
 	}
+
+	/* disable RDSEED on AMD Cyan Skillfish because of hw bug */
+	if (c->x86_vendor == X86_VENDOR_AMD && c->x86 == 0x17 &&
+	    c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
+	}
 }
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index e6134ef2263d..8b48a54b627a 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -616,6 +616,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
-- 
2.49.0

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Borislav Petkov]

On Sat, May 24, 2025 at 05:53:19PM +0300, Mikhail Paulyshka wrote:
> AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an
> error that causes RDSEED to always return 0xffffffff, while RDRAND
> works correctly.
> 
> This patch masks the RDSEED cap for this CPU so that both

s/This patch masks/Mask/

> /proc/cpuinfo and direct CPUID read report RDSEED as unavailable.
> 
> 
> v2:
>   * Limit changes to AMD Cyan Skillfish
>   * Replace the runtime RDSEED sanity check with a simple
>     family/model/stepping match

Changelog stuff goes...

> 
> Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
> ---

<--- ... here, under the "---" so that patch handling scripts can ignore it.

>  arch/x86/include/asm/msr-index.h       | 1 +
>  arch/x86/kernel/cpu/rdrand.c           | 9 +++++++++
>  tools/arch/x86/include/asm/msr-index.h | 1 +
>  3 files changed, 11 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index e7d2f460fcc6..2333f4e7bc2f 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -624,6 +624,7 @@
>  #define MSR_AMD64_OSVW_STATUS		0xc0010141
>  #define MSR_AMD_PPIN_CTL		0xc00102f0
>  #define MSR_AMD_PPIN			0xc00102f1
> +#define MSR_AMD64_CPUID_FN_7		0xc0011002
>  #define MSR_AMD64_CPUID_FN_1		0xc0011004
>  #define MSR_AMD64_LS_CFG		0xc0011020
>  #define MSR_AMD64_DC_CFG		0xc0011022
> diff --git a/arch/x86/kernel/cpu/rdrand.c b/arch/x86/kernel/cpu/rdrand.c
> index eeac00d20926..c474d0a5c317 100644
> --- a/arch/x86/kernel/cpu/rdrand.c
> +++ b/arch/x86/kernel/cpu/rdrand.c
> @@ -11,6 +11,7 @@
>  #include <asm/processor.h>
>  #include <asm/archrandom.h>
>  #include <asm/sections.h>
> +#include <asm/msr.h>
>  
>  /*
>   * RDRAND has Built-In-Self-Test (BIST) that runs on every invocation.
> @@ -47,4 +48,12 @@ void x86_init_rdrand(struct cpuinfo_x86 *c)
>  		clear_cpu_cap(c, X86_FEATURE_RDSEED);
>  		pr_emerg("RDRAND is not reliable on this platform; disabling.\n");
>  	}
> +
> +	/* disable RDSEED on AMD Cyan Skillfish because of hw bug */

Not a hw bug - "... has an error" above was closer :-)

> +	if (c->x86_vendor == X86_VENDOR_AMD && c->x86 == 0x17 &&
> +	    c->x86_model == 0x47 && c->x86_stepping == 0x0) {
> +		clear_cpu_cap(c, X86_FEATURE_RDSEED);
> +		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
> +		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
> +	}
>  }
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index e6134ef2263d..8b48a54b627a 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -616,6 +616,7 @@
>  #define MSR_AMD64_OSVW_STATUS		0xc0010141
>  #define MSR_AMD_PPIN_CTL		0xc00102f0
>  #define MSR_AMD_PPIN			0xc00102f1
> +#define MSR_AMD64_CPUID_FN_7		0xc0011002
>  #define MSR_AMD64_CPUID_FN_1		0xc0011004
>  #define MSR_AMD64_LS_CFG		0xc0011020
>  #define MSR_AMD64_DC_CFG		0xc0011022
> -- 

In any case, those are just minor nits which can be dealt with when applying.

Otherwise, patch looks good, thanks.

We have merge window upcoming next week so I'll take it after that but it is
on my list of patches to take after the MW.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Borislav Petkov]

On Sat, May 24, 2025 at 05:53:19PM +0300, Mikhail Paulyshka wrote:
> AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an
> error that causes RDSEED to always return 0xffffffff, while RDRAND
> works correctly.
> 
> This patch masks the RDSEED cap for this CPU so that both
> /proc/cpuinfo and direct CPUID read report RDSEED as unavailable.
> 
> 
> v2:
>   * Limit changes to AMD Cyan Skillfish
>   * Replace the runtime RDSEED sanity check with a simple
>     family/model/stepping match
> 
> Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
> ---
>  arch/x86/include/asm/msr-index.h       | 1 +
>  arch/x86/kernel/cpu/rdrand.c           | 9 +++++++++
>  tools/arch/x86/include/asm/msr-index.h | 1 +
>  3 files changed, 11 insertions(+)

Does this one work too?

---
From: Mikhail Paulyshka <me@mixaill.net>
Date: Sat, 24 May 2025 17:53:19 +0300
Subject: [PATCH] x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an error that
causes RDSEED to always return 0xffffffff, while RDRAND works correctly.

Mask the RDSEED cap for this CPU so that both /proc/cpuinfo and direct CPUID
read report RDSEED as unavailable.

  [ bp: Move to amd.c, massage. ]

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250524145319.209075-1-me@mixaill.net
---
 arch/x86/include/asm/msr-index.h       | 1 +
 arch/x86/kernel/cpu/amd.c              | 7 +++++++
 tools/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c8113..5cfb5d74dd5f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 93da466dfe2c..c2ef5ab4a9e3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -930,6 +930,13 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 	zen2_zenbleed_check(c);
+
+	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */
+	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
+	}
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index e7d2f460fcc6..2333f4e7bc2f 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -624,6 +624,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
-- 
2.43.0

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Dave Hansen]

On 6/17/25 13:05, Borislav Petkov wrote:
> +	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */
> +	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
> +		clear_cpu_cap(c, X86_FEATURE_RDSEED);
> +		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
> +		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
> +	}

Heh, maybe if x86_init_rdrand() did RDSEED too, this wouldn't have
slipped through QA.

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Mikhail Paulyshka]

On 6/17/25 11:05 PM, Borislav Petkov wrote:
> Does this one work too?

It works, however, there is another issue with the BC250 that appeared 
since Linux 6.15.

Commit 4afeb0ed1753ebcad93ee3b45427ce85e9c8ec40 ( x86/mm: Enable 
broadcast TLB invalidation for multi-threaded processes)[1], merged in 
Linux 6.15-rc1, breaks the device — it starts to oops and panic under 
any load [2].

[1] 
https://docs.google.com/spreadsheets/d/1kJleOY5k-YREGak1pQhVWIGckA9YA3OWJyCbybZbk00/edit?gid=0#gid=0
[2] https://mixaill.net/linux-kernel-lists/bc250_log_invlpgb-1.txt

Clearing the X86_FEATURE_INVLPGB cap helps and the device works normally 
again.

It would be great to have this change backported to 6.15 and 6.16 as the 
device is currently unstable with these kernels.

---
 From 064c91c5f3fc02a6eecd6b0b7cf074e2d0eb75aa Mon Sep 17 00:00:00 2001
From: Mikhail Paulyshka <me@mixaill.net>
Date: Sun, 6 Jul 2025 01:46:46 +0300
Subject: [PATCH 2/2] x86/cpu/amd: disable INVLPGB on AMD Cyan Skillfish

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an issue that
causes system oopses and panics when performing TLB flush using INVLPGB.

Clearing the X86_FEATURE_INVLPGB flag restoring system stability.

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
---
  arch/x86/kernel/cpu/amd.c | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 21072f84071a..89b74203396e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -935,6 +935,12 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
          msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
          pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
      }
+
+    /* Disable INVLPGB on AMD Cyan Skillfish because of an error */
+    if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+        clear_cpu_cap(c, X86_FEATURE_INVLPGB);
+        pr_emerg("INVLPGB is not reliable on this platform; disabling.\n");
+    }
  }

  static void init_amd_zen3(struct cpuinfo_x86 *c)
-- 
2.50.0

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Borislav Petkov]

On Sun, Jul 06, 2025 at 07:42:39PM +0300, Mikhail Paulyshka wrote:
> On 6/17/25 11:05 PM, Borislav Petkov wrote:
> > Does this one work too?
> 
> It works, however, there is another issue with the BC250 that appeared since
> Linux 6.15.
> 
> Commit 4afeb0ed1753ebcad93ee3b45427ce85e9c8ec40 ( x86/mm: Enable broadcast
> TLB invalidation for multi-threaded processes)[1], merged in Linux 6.15-rc1,
> breaks the device — it starts to oops and panic under any load [2].

Looks like it GPs because CR4.PCID == 0.

Looks weird, we need to check PCID support somewhere, it seems.

Ok, let's get a common code base - 6.15. Pls boot it, send me full dmesg
again, your .config and the output of

cpuid -1r

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Mikhail Paulyshka]

On 7/6/25 8:07 PM, Borislav Petkov wrote:
> Looks like it GPs because CR4.PCID == 0.
>
> Looks weird, we need to check PCID support somewhere, it seems.
>
> Ok, let's get a common code base - 6.15. Pls boot it, send me full dmesg again

dmesg with vanilla 6.15.0:
https://mixaill.net/linux-kernel-lists/bc250_log_invlpgb-2-dmesg.txt

>   your .config
https://raw.githubusercontent.com/openSUSE/kernel-source/4552ba89cbebd55482508c4ba4fc290df58f9386/config/x86_64/vanilla
>   and the output of cpuid -1r
https://mixaill.net/linux-kernel-lists/bc250_log_invlpgb-2-cpuid.txt

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Mikhail Paulyshka]

On 6/17/25 11:21 PM, Dave Hansen wrote:
> Heh, maybe if x86_init_rdrand() did RDSEED too, this wouldn't have
> slipped through QA.

This might be interesting to you: in V1 of this patch set, there was an 
RDSEED sanity check, and Intel's CI detected broken RDSEED on Comet Lake:

https://lore.kernel.org/all/202503211421.fc83271a-lkp@intel.com/

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Borislav Petkov]

On Mon, Jul 07, 2025 at 01:17:41PM +0300, Mikhail Paulyshka wrote:
> On 6/17/25 11:21 PM, Dave Hansen wrote:
> > Heh, maybe if x86_init_rdrand() did RDSEED too, this wouldn't have
> > slipped through QA.
> 
> This might be interesting to you: in V1 of this patch set, there was an
> RDSEED sanity check, and Intel's CI detected broken RDSEED on Comet Lake:
> 
> https://lore.kernel.org/all/202503211421.fc83271a-lkp@intel.com/

Right, I'm being told this is preproduction hw:

[    2.823625][    T1] smpboot: CPU0: Genuine Intel(R) CPU 0000 @ 3.30GHz (family: 0x6, model: 0xa5, stepping: 0x1)

and strictly speaking, RDSEED *can* fail due to resources exhaustion etc
- doesn't necessarily mean it is broken.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v2 1/1] x86/rdrand: disable RDSEED on AMD Cyan Skillfish

[Dave Hansen]

On 7/7/25 03:17, Mikhail Paulyshka wrote:
> On 6/17/25 11:21 PM, Dave Hansen wrote:
>> Heh, maybe if x86_init_rdrand() did RDSEED too, this wouldn't have
>> slipped through QA.
> 
> This might be interesting to you: in V1 of this patch set, there was an
> RDSEED sanity check, and Intel's CI detected broken RDSEED on Comet Lake:
> 
> https://lore.kernel.org/all/202503211421.fc83271a-lkp@intel.com/

Just to be clear, I'd call that *A* Comet Lake system. Saying it's
"broken on Comet Lake" kinda implies that they're all broken.

I'd definitely want to rule out a single wonky system first, like it
being on some old weird microcode.

[tip: x86/urgent] x86/CPU/AMD: Disable INVLPGB on Zen2

[tip-bot2 for Mikhail Paulyshka]

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     5a97aa3a4f1f19656aea5c76c1da66ce9dc5ddaf
Gitweb:        https://git.kernel.org/tip/5a97aa3a4f1f19656aea5c76c1da66ce9dc5ddaf
Author:        Mikhail Paulyshka <me@mixaill.net>
AuthorDate:    Tue, 08 Jul 2025 16:39:10 +02:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Tue, 08 Jul 2025 16:41:59 +02:00

x86/CPU/AMD: Disable INVLPGB on Zen2

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an issue
that causes system oopses and panics when performing TLB flush using
INVLPGB.

However, the problem is that that machine has misconfigured CPUID and
should not report the INVLPGB bit in the first place. So zap the
kernel's representation of the flag so that nothing gets confused.

  [ bp: Massage. ]

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/1ebe845b-322b-4929-9093-b41074e9e939@mixaill.net
---
 arch/x86/kernel/cpu/amd.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e1c4661..1b1ff60 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -937,6 +937,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
 		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
 	}
+
+	/* Correct misconfigured CPUID on some clients. */
+	clear_cpu_cap(c, X86_FEATURE_INVLPGB);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

[tip: x86/urgent] x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

[tip-bot2 for Mikhail Paulyshka]

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     dc562662cb2b0bcc7af4ca3cd53e6140ff52a418
Gitweb:        https://git.kernel.org/tip/dc562662cb2b0bcc7af4ca3cd53e6140ff52a418
Author:        Mikhail Paulyshka <me@mixaill.net>
AuthorDate:    Sat, 24 May 2025 17:53:19 +03:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Tue, 08 Jul 2025 16:26:42 +02:00

x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an error that
causes RDSEED to always return 0xffffffff, while RDRAND works correctly.

Mask the RDSEED cap for this CPU so that both /proc/cpuinfo and direct CPUID
read report RDSEED as unavailable.

  [ bp: Move to amd.c, massage. ]

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250524145319.209075-1-me@mixaill.net
---
 arch/x86/include/asm/msr-index.h       | 1 +
 arch/x86/kernel/cpu/amd.c              | 7 +++++++
 tools/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3..5cfb5d7 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 655f44f..e1c4661 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -930,6 +930,13 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 	zen2_zenbleed_check(c);
+
+	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */
+	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
+	}
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index b7dded3..5cfb5d7 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022

[tip: x86/urgent] x86/CPU/AMD: Disable INVLPGB on Zen2

[tip-bot2 for Mikhail Paulyshka]

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     a74bb5f202dabddfea96abc1328fcedae8aa140a
Gitweb:        https://git.kernel.org/tip/a74bb5f202dabddfea96abc1328fcedae8aa140a
Author:        Mikhail Paulyshka <me@mixaill.net>
AuthorDate:    Tue, 08 Jul 2025 16:39:10 +02:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Tue, 08 Jul 2025 21:34:01 +02:00

x86/CPU/AMD: Disable INVLPGB on Zen2

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an issue
that causes system oopses and panics when performing TLB flush using
INVLPGB.

However, the problem is that that machine has misconfigured CPUID and
should not report the INVLPGB bit in the first place. So zap the
kernel's representation of the flag so that nothing gets confused.

  [ bp: Massage. ]

Fixes: 767ae437a32d ("x86/mm: Add INVLPGB feature and Kconfig entry")
Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/1ebe845b-322b-4929-9093-b41074e9e939@mixaill.net
---
 arch/x86/kernel/cpu/amd.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e1c4661..1b1ff60 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -937,6 +937,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
 		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
 	}
+
+	/* Correct misconfigured CPUID on some clients. */
+	clear_cpu_cap(c, X86_FEATURE_INVLPGB);
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)

[tip: x86/urgent] x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

[tip-bot2 for Mikhail Paulyshka]

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     5b937a1ed64ebeba8876e398110a5790ad77407c
Gitweb:        https://git.kernel.org/tip/5b937a1ed64ebeba8876e398110a5790ad77407c
Author:        Mikhail Paulyshka <me@mixaill.net>
AuthorDate:    Sat, 24 May 2025 17:53:19 +03:00
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Tue, 08 Jul 2025 21:33:26 +02:00

x86/rdrand: Disable RDSEED on AMD Cyan Skillfish

AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an error that
causes RDSEED to always return 0xffffffff, while RDRAND works correctly.

Mask the RDSEED cap for this CPU so that both /proc/cpuinfo and direct CPUID
read report RDSEED as unavailable.

  [ bp: Move to amd.c, massage. ]

Signed-off-by: Mikhail Paulyshka <me@mixaill.net>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/20250524145319.209075-1-me@mixaill.net
---
 arch/x86/include/asm/msr-index.h       | 1 +
 arch/x86/kernel/cpu/amd.c              | 7 +++++++
 tools/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3..5cfb5d7 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 655f44f..e1c4661 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -930,6 +930,13 @@ static void init_amd_zen2(struct cpuinfo_x86 *c)
 	init_spectral_chicken(c);
 	fix_erratum_1386(c);
 	zen2_zenbleed_check(c);
+
+	/* Disable RDSEED on AMD Cyan Skillfish because of an error. */
+	if (c->x86_model == 0x47 && c->x86_stepping == 0x0) {
+		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");
+	}
 }
 
 static void init_amd_zen3(struct cpuinfo_x86 *c)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index b7dded3..5cfb5d7 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -628,6 +628,7 @@
 #define MSR_AMD64_OSVW_STATUS		0xc0010141
 #define MSR_AMD_PPIN_CTL		0xc00102f0
 #define MSR_AMD_PPIN			0xc00102f1
+#define MSR_AMD64_CPUID_FN_7		0xc0011002
 #define MSR_AMD64_CPUID_FN_1		0xc0011004
 #define MSR_AMD64_LS_CFG		0xc0011020
 #define MSR_AMD64_DC_CFG		0xc0011022