From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D8D322D4DB; Thu, 29 May 2025 13:35:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525716; cv=none; b=eJTyKUrgNT9/ykkfCe+zj9Uk6ngdtbZUDg+8zk/6xC51Ooe9c68hKDkWsHgpqaqyeo/kqNO4zUlBcheVd2e1oROhT0YfQhTTUpUBhUbi9S9/lVFTTiHnd3a+q65qC4XxI+/Jbn3KmDPtyW26atMCNvhIrzNcv4wPLJMXaeqOww4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525716; c=relaxed/simple; bh=G1o761x7CvwA9g+7zfleh+xX9V2mAumko5AUVzpjSXE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RCMA3m3bydYP5HNT+nUVLEl8Lzqbgu30KPO2MfxFO/DLoM+PRPPfhFwu6cqQ4bwSgs2Q8+EXSOQ7JRH4bYLbf3bsn9Hm9j9a+4gzv1a6ylQ2BlIptUuKqwrDuLFIr/ZjkmdhOpGLB3jXnzpo2Q2CSwSS67bE16r5NqlICR7RPUc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=gGTTK7Od; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gGTTK7Od" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZ9n72407092; Thu, 29 May 2025 08:35:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525709; bh=5k6/noStFDeQw/83+ecH4/M9IJRXnI3sitFb7DXoocs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gGTTK7OdAE6ow/SvXTXJYkMCn0WG7S9gy1vmbx7vPDClPr7umK6ETSCKKXuFQaF2G Q3jpvwEsAzNFiqGXl/sXW8dGohokZpe04T33NoQFzNv/NxNYpVEHpw8Ttc+Ex2s8Xl jCteA9AaBLOx8cZ/HxP0Pit4T2R3Yda4+pL3zmWU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZ9eD126584 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:09 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:08 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:08 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8m1650971; Thu, 29 May 2025 08:35:05 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 06/13] arm64: dts: ti: k3-am65-mcu: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:36 +0530 Message-ID: <20250529133443.1252293-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 7cf1f646500a..cd0b796c5f8f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -354,6 +354,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; -- 2.34.1