From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: "Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>,
linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/4] media: rcar-csi2: Rework macros to access AFE lanes
Date: Fri, 30 May 2025 16:06:28 +0300 [thread overview]
Message-ID: <20250530130628.GB18205@pendragon.ideasonboard.com> (raw)
In-Reply-To: <20250511174730.944524-3-niklas.soderlund+renesas@ragnatech.se>
On Sun, May 11, 2025 at 07:47:28PM +0200, Niklas Söderlund wrote:
> Each AFE lane have a set of control and offset registers. The registers
s/have/has/
> themself are undocumented but later datasheets program more of them with
> magic values. Before exploding the driver with more defines to name them
> all rework the AFE ones to be able to address all controls and offsets.
>
> Also move a stray define that is out of sequence.
>
> There is no functional change.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> * Changes since v1
> - Adjust line length.
> ---
> drivers/media/platform/renesas/rcar-csi2.c | 32 +++++++++++-----------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c
> index 358e7470befc..cdd358b4a973 100644
> --- a/drivers/media/platform/renesas/rcar-csi2.c
> +++ b/drivers/media/platform/renesas/rcar-csi2.c
> @@ -177,15 +177,14 @@ struct rcar_csi2;
> #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0
>
> /* V4H CORE registers */
> -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */
> -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */
> -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */
> -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */
> -#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */
> +
> +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0x22040 + ((l) * 0x400) + ((n) * 2))
> +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0x22060 + ((l) * 0x400) + ((n) * 2))
> +#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0x22080 + ((l) * 0x400) + ((n) * 2))
> +
> #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */
> #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */
> #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */
> -#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
>
> /* V4H C-PHY */
> #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */
> @@ -197,6 +196,7 @@ struct rcar_csi2;
> #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
> #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480
> #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */
> +#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
> #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800
> #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880
> #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */
> @@ -1246,11 +1246,11 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps)
> rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2);
> rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2);
>
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001);
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0);
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001);
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001);
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 2), 0x0001);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 2), 0);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 2), 0x0001);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(3, 2), 0x0001);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(4, 2), 0);
>
> rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0);
> rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0);
> @@ -1267,13 +1267,13 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps)
> /* Configure data line order. */
> rsci2_set_line_order(priv, priv->line_orders[0],
> V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG,
> - V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9));
> + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9));
> rsci2_set_line_order(priv, priv->line_orders[1],
> V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG,
> - V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(9));
> + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(1, 9));
> rsci2_set_line_order(priv, priv->line_orders[2],
> V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG,
> - V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(9));
> + V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(2, 9));
>
> /* TODO: This registers is not documented. */
> rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000);
> @@ -1289,8 +1289,8 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int mbps)
> }
>
> /* C-PHY setting - analog programing*/
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9), conf->lane29);
> - rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(7), conf->lane27);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 9), conf->lane29);
> + rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(0, 7), conf->lane27);
>
> return 0;
> }
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-05-30 13:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-11 17:47 [PATCH v2 0/4] media: rcar-csi2: Add D-PHY support for V4H Niklas Söderlund
2025-05-11 17:47 ` [PATCH v2 1/4] media: rcar-csi2: Clarify usage of mbps and msps Niklas Söderlund
2025-05-30 12:31 ` Tomi Valkeinen
2025-05-30 13:04 ` Laurent Pinchart
2025-05-11 17:47 ` [PATCH v2 2/4] media: rcar-csi2: Rework macros to access AFE lanes Niklas Söderlund
2025-05-30 13:06 ` Laurent Pinchart [this message]
2025-05-11 17:47 ` [PATCH v2 3/4] media: rcar-csi2: Update start procedure for V4H Niklas Söderlund
2025-05-30 13:42 ` Laurent Pinchart
2025-05-11 17:47 ` [PATCH v2 4/4] media: rcar-csi2: Add D-PHY support " Niklas Söderlund
2025-05-11 19:07 ` ALOK TIWARI
2025-05-11 20:03 ` Niklas Söderlund
2025-05-12 7:37 ` Geert Uytterhoeven
2025-05-12 8:48 ` Niklas Söderlund
2025-05-30 13:38 ` Laurent Pinchart
2025-05-30 12:31 ` [PATCH v2 0/4] " Tomi Valkeinen
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