From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A15A91AF0BF; Sun, 1 Jun 2025 23:27:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748820472; cv=none; b=F9z9LRWZ4Rq4+WS6PtAP6vIEoveY9PQwBRNDoNjdxOQ0Tp2Yhb9drVtiIjxnBCYQZt7k/D0B8j/63femNXKiVC2Zn4UiucfXihBVjFiqzgluz2zypTBFDQpTw2u+960qv9H5QyQJNN5EeNgPM6J6mVeYzTrNWjuePu2qIK/+IPg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748820472; c=relaxed/simple; bh=Hi+u6xACvnljfk+RoXAgBNCMsFdimHTuU7lAQgjM7oo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ffehxos2YXux06qkyiiLtPs5sbb6b8N3iHJRaOyOJ9bfiQyB8pWqvHMw+nXTCVDyQpU12MO7JkAttSJVd5sSi208sUwgAFc9l6AhZizJwD2pgYWbZEh6EpL+oGimABqNUfMS7WmC77gHQ+pohUQcsDk2D3g8hSTTwLUCMuCir4k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GdLMQCtq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GdLMQCtq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A9AADC4CEF1; Sun, 1 Jun 2025 23:27:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748820472; bh=Hi+u6xACvnljfk+RoXAgBNCMsFdimHTuU7lAQgjM7oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GdLMQCtq4zAIH5qL7xz4S7bno4uROErJyPpn89M1Q8pHvL3mYut5E2MQYrAxaHVGP TxbEOaW1sWPevOmhtIMzf509JzJxu3nJU7d52bXCdq4zv5SAf9m8ffaaQBjUdr8exc nVdueQyDqVv7e7s3n4xPgFmZsXFJiA0P4exWlBkAsjEb/+d9gWewtoopiQN1M8Fhml 4xwgT2dbJl3iaYiytqzs3fRJ6Xf86O14bC0fdhgcZxkInoTE+HOoRsX/qQeHXmlq0m XaLZ9BXzVd7A+e1iaPvb7EwlAEMZgjHaeIORgxqDjF4pSPprBvOLeh7rZgviObHJWG mIvfmBwO2GyZQ== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: TungYu Lu , Nicholas Kazlauskas , Zaeem Mohamed , Mark Broadworth , Alex Deucher , Sasha Levin , austin.zheng@amd.com, jun.lei@amd.com, harry.wentland@amd.com, sunpeng.li@amd.com, christian.koenig@amd.com, airlied@gmail.com, simona@ffwll.ch, alex.hung@amd.com, rodrigo.siqueira@amd.com, v.shevtsov@mt-integration.ru, alvin.lee2@amd.com, hamzamahfooz@linux.microsoft.com, ivlipski@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH AUTOSEL 6.15 065/110] drm/amd/display: Correct prefetch calculation Date: Sun, 1 Jun 2025 19:23:47 -0400 Message-Id: <20250601232435.3507697-65-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250601232435.3507697-1-sashal@kernel.org> References: <20250601232435.3507697-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.15 Content-Transfer-Encoding: 8bit From: TungYu Lu [ Upstream commit 33bc89949b4366dff2dca30bc61ba1c0cbcd2ab2 ] [Why] The minimum value of the dst_y_prefetch_equ was not correct in prefetch calculation whice causes OPTC underflow. [How] Add the min operation of dst_y_prefetch_equ in prefetch calculation for legacy DML. Reviewed-by: Nicholas Kazlauskas Signed-off-by: TungYu Lu Signed-off-by: Zaeem Mohamed Tested-by: Mark Broadworth Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- **YES** ## Analysis This commit should be backported to stable kernel trees. Here's my detailed analysis: ### **Bug Description and Impact** The commit fixes a critical hardware register overflow issue in AMD display's prefetch calculation that causes OPTC (Output Pipe and Timing Control) underflow. OPTC underflow is a serious display issue that can cause: - Screen corruption or artifacts - Display timing problems - Potential system instability during display operations ### **Code Change Analysis** The fix adds a single line in three DCN (Display Core Next) versions (30, 31, 314): ```c dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH ``` This change: 1. **Prevents register overflow**: The DST_Y_PREFETCH register is limited to 8 bits with U6.2 format, meaning maximum value is 63.75 2. **Applies early in calculation**: The limit is applied to `dst_y_prefetch_equ` before it's used in subsequent calculations 3. **Matches existing pattern**: DCN21 already has this exact fix (commit 9857bb9457fe5 from 2021), establishing this as a known, proven solution ### **Why This Should Be Backported** 1. **Important Bug Fix**: Fixes a hardware register overflow that causes visible display issues affecting end users 2. **Minimal Risk**: - Single line addition in each file - No architectural changes - Simply enforces hardware register limits that should have been there - Proven safe (already in DCN21 for 3+ years) 3. **Contained Scope**: Only affects AMD display prefetch calculations in legacy DML (Display Mode Library) versions 4. **Clear User Impact**: OPTC underflow causes noticeable display problems that users would report 5. **Follows Stable Criteria**: - Small, obvious fix - Addresses hardware limitation - Low regression risk - Similar to reference commits marked "YES" for backporting ### **Comparison with Similar Commits** Looking at the provided examples: - **Similar Commit #1** (YES): Also fixes prefetch calculation with min operation and has `Cc: stable@vger.kernel.org` - **Similar Commit #2** (YES): Fixes prefetch calculation loop variables and explicitly tagged for stable backport - **Similar Commit #4** (NO): Same type of DST_Y_PREFETCH guard fix but wasn't tagged for stable The pattern shows that prefetch calculation fixes that prevent register overflow and have clear user impact are good backport candidates. ### **Hardware Context** This affects DCN 3.0, 3.1, and 3.14 hardware generations. The fact that DCN 2.1 already had this fix suggests this was a systematic issue across multiple hardware generations that needed addressing. The fix is essential for proper display functionality and represents a critical hardware constraint that must be enforced to prevent register overflow and subsequent display corruption. drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 1 + drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 1 + drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index f1fe49401bc0a..8d24763938ea6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -1002,6 +1002,7 @@ static bool CalculatePrefetchSchedule( dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); + dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC); Tsw_oto = Lsw_oto * LineTime; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index f567a9023682d..ed59c77bc6f60 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -1105,6 +1105,7 @@ static bool CalculatePrefetchSchedule( Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto; dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); + dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0; Tpre_rounded = dst_y_prefetch_equ * LineTime; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 5865e8fa2d8e8..9f3938a50240f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -1123,6 +1123,7 @@ static bool CalculatePrefetchSchedule( Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto; dst_y_prefetch_equ = VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); + dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0; Tpre_rounded = dst_y_prefetch_equ * LineTime; -- 2.39.5