[PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

[PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

[E Shattow]

Bring in additional downstream U-Boot boot loader changes for StarFive
VisionFive2 board target (and related JH7110 common boards). There is a
memory controller with no downstream dt-binding; create a basic dt-binding
(and not any Linux driver) in support of the memory-controller dts node
needed by U-Boot starfive_ddr.c driver. Also add bootph-pre-ram hinting
to jh7110.dtsi needed at SPL boot phase.

Changes since RFC:

- Drop additional timer node from series as not strictly needed for boot.
- Add patch for starfive,jh7110-dmc binding
- Adjust ordering of bootph-pre-ram hints to follow devicetree style guide

E Shattow (3):
  dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
  riscv: dts: starfive: jh7110: add memory controller node
  riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
    loader

 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 22 ++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml


base-commit: d50108706a63dfd896db42172bf9f6aebec219c5
-- 
2.49.0

[PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[E Shattow]

Document bindings for the JH7110 SoC DMC as implemented in downstream
U-Boot driver starfive_ddr.c

Signed-off-by: E Shattow <e@freeshell.de>
---
 .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
new file mode 100644
index 000000000000..299c86893db1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <e@freeshell.de>
+
+description:
+  JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll1_out
+
+  clock-frequency:
+    enum: [2133, 2800]
+    default: 2133
+
+  resets:
+    minItems: 3
+    maxItems: 3
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-frequency
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memory-controller@15700000 {
+        compatible = "starfive,jh7110-dmc";
+        reg = <0x0 0x15700000 0x0 0x10000>,
+              <0x0 0x13000000 0x0 0x10000>;
+        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+        clock-names = "pll1_out";
+        clock-frequency = <2133>;
+        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                 <&syscrg JH7110_SYSRST_DDR_OSC>,
+                 <&syscrg JH7110_SYSRST_DDR_APB>;
+        reset-names = "axi", "osc", "apb";
+      };
+    };
-- 
2.49.0

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[Krzysztof Kozlowski]

On 06/06/2025 15:02, E Shattow wrote:
> Document bindings for the JH7110 SoC DMC as implemented in downstream
> U-Boot driver starfive_ddr.c
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> new file mode 100644
> index 000000000000..299c86893db1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 DMC
> +
> +maintainers:
> +  - E Shattow <e@freeshell.de>
> +
> +description:
> +  JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c

Bindings are about hardware. Explain the hardware, not drivers.

> +
> +properties:
> +  compatible:
> +    items:
> +      - const: starfive,jh7110-dmc
> +
> +  reg:
> +    minItems: 2

Drop

> +    maxItems: 2

Drop and list items with description instead


> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: pll1_out
> +
> +  clock-frequency:
> +    enum: [2133, 2800]
> +    default: 2133

Drop clock-frequency. I doubt 2133 Hz is even correct... This is a
legacy property, use common clock framework.

> +
> +  resets:
> +    minItems: 3
> +    maxItems: 3

List the items with description instead

> +
> +  reset-names:
> +    items:
> +      - const: axi
> +      - const: osc
> +      - const: apb
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - clock-frequency
> +  - resets
> +  - reset-names
Best regards,
Krzysztof

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[Krzysztof Kozlowski]

On 06/06/2025 15:02, E Shattow wrote:
> Document bindings for the JH7110 SoC DMC as implemented in downstream
> U-Boot driver starfive_ddr.c

Heh, I totally missed "downstream"... We do not add bindings for
downstream. We do not care about downstream, so I should not spend my
time on this.

Do not send code for downstream.

Best regards,
Krzysztof

Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[Conor Dooley]

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On Mon, Jun 23, 2025 at 08:45:04AM +0200, Krzysztof Kozlowski wrote:
> On 06/06/2025 15:02, E Shattow wrote:
> > Document bindings for the JH7110 SoC DMC as implemented in downstream
> > U-Boot driver starfive_ddr.c
> 
> Heh, I totally missed "downstream"... We do not add bindings for
> downstream. We do not care about downstream, so I should not spend my
> time on this.
> 
> Do not send code for downstream.

I think that's either an accident or poor wording, there's a user for
this in mainline U-Boot.

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Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[Krzysztof Kozlowski]

On 23/06/2025 17:56, Conor Dooley wrote:
> On Mon, Jun 23, 2025 at 08:45:04AM +0200, Krzysztof Kozlowski wrote:
>> On 06/06/2025 15:02, E Shattow wrote:
>>> Document bindings for the JH7110 SoC DMC as implemented in downstream
>>> U-Boot driver starfive_ddr.c
>>
>> Heh, I totally missed "downstream"... We do not add bindings for
>> downstream. We do not care about downstream, so I should not spend my
>> time on this.
>>
>> Do not send code for downstream.
> 
> I think that's either an accident or poor wording, there's a user for
> this in mainline U-Boot.


OK, then my review stays. Commit msg should be rephrased.

In future: bindings always should be accepted prior other project starts
accepting drivers (just in case if you plan to play Uno card called:
"but my driver is like that").

Best regards,
Krzysztof

[PATCH v1 2/3] riscv: dts: starfive: jh7110: add memory controller node

[E Shattow]

add memory controller node used downstream by U-Boot boot loader.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0ba74ef04679..6fdeac3e0aff 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -372,6 +372,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.49.0

[PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[E Shattow]

Add bootph-pre-ram hinting to jh7110.dtsi:
  - CPU interrupt controller(s)
  - core local interrupt timer
  - DDR memory controller
  - oscillator
  - syscrg clock-controller

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 6fdeac3e0aff..8a56e8b91b61 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -35,6 +35,7 @@ S7_0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -68,6 +69,7 @@ U74_1: cpu@1 {
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -101,6 +103,7 @@ U74_2: cpu@2 {
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -134,6 +137,7 @@ U74_3: cpu@3 {
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -167,6 +171,7 @@ U74_4: cpu@4 {
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
 
 	osc: oscillator {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "osc";
 		#clock-cells = <0>;
 	};
@@ -354,6 +360,7 @@ soc {
 		clint: timer@2000000 {
 			compatible = "starfive,jh7110-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,
@@ -376,6 +383,7 @@ memory-controller@15700000 {
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
 			clock-names = "pll1_out";
 			clock-frequency = <2133>;
@@ -893,6 +901,7 @@ qspi: spi@13010000 {
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&osc>, <&gmac1_rmii_refin>,
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
-- 
2.49.0