From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C821F258CF2; Mon, 9 Jun 2025 12:23:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749471803; cv=none; b=TxrAQNkBSxPJ4eM3hhaU93TTwa27U90phu6ws2AVvGolhv0lCPHI0aXK7CRfMt7fT0liIGUz6vMp/JZTjC5WcpToy1OO1nlbPRNC1VwXg413broLUKo3ltVNk3NGPW0CSuphEYfI/OO+p4D8UXvTtnMcC555hbtvrEMqOnuUoYI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749471803; c=relaxed/simple; bh=kRLC6ZZo+VAu2oCBPPJYpQlT3f436/w8PHqXyuwMODM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jghkzDq50ZJECoulPOgz/+Na3hXaXIvzITqYyKqKzDx/7t+pHgFzG/cjSL5u3xjBEuTvWnCRixoerbU4VwfkVWiapAq/FtTQNjSKuiaImvXn0FO9b1h89M3RlYR4ygUDghTko7CLlkOSrlZD8ghdWXkcV+wYm8oFYwuttG9lTRI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=eAdvMmAH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="eAdvMmAH" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55993Oud006202; Mon, 9 Jun 2025 12:22:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4C6JpqDqluzvHitt30tOMhtcKhDVpBOzpqWDWZC8YjA=; b=eAdvMmAHxotSKNnp W3O0dmpGDC8I0o2pRQAJ5FVYeulb561uJ/pN18k7xU5HgRoXX62kHTi9jw/Pd5Tj giRSnWrCEDzDCFLOurM3h8A1uPDInLsQXAYZ2bxDk5ZMh/yRV7k5eTkmQj+LVAEw DWluHT+4+0uj2BEOBxVk5AMAmM51mpfUHCR+kBpvsDMtPX/kU1DF1MYhjeSHapRl SAGrfpbSXMOWrb/pTd71DqaFTZszgTrjFttm7HgkKhawnlHB2/QQoayIvJCByW3J gxH8qqczd8/YwkEASkQtFZc3iMxmKklNf+/PfRc4xhqOLM3tLGJjMlj8d1xrRBVN XezCGg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 474dgxpacy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 09 Jun 2025 12:22:58 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 559CMvqh002158 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Jun 2025 12:22:57 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Jun 2025 05:22:53 -0700 From: Yongxing Mou Date: Mon, 9 Jun 2025 20:21:21 +0800 Subject: [PATCH v2 02/38] drm/msm/dp: remove dp_display's dp_mode and use dp_panel's instead Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250609-msm-dp-mst-v2-2-a54d8902a23d@quicinc.com> References: <20250609-msm-dp-mst-v2-0-a54d8902a23d@quicinc.com> In-Reply-To: <20250609-msm-dp-mst-v2-0-a54d8902a23d@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , , "Yongxing Mou" , Abhinav Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749471753; l=5649; i=quic_yongmou@quicinc.com; s=20241121; h=from:subject:message-id; bh=fcX8WU9PFVR2nu/XCB9033d3n7fbxY9Lrc6HfSgt9vY=; b=qqs5cm8e8E6R2JFbIA3JEEZKRWStGAL1kUMHPgNMs95kPqiodHrpkAX/BwVZ2g1m5MudLkJx5 r67fSFo/QyVBvvxKvLcUI1WyuEE2ge0VtQo0Uu7QItJjY2jmtMYL+aw X-Developer-Key: i=quic_yongmou@quicinc.com; a=ed25519; pk=zeCnFRUqtOQMeFvdwex2M5o0Yf67UHYfwCyBRQ3kFbU= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: lM9bnwqrDGwHOgg-AmCfCN3JkrYa3Q5z X-Authority-Analysis: v=2.4 cv=HMbDFptv c=1 sm=1 tr=0 ts=6846d222 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=nlSEVkDa0a8GYKyVT-EA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: lM9bnwqrDGwHOgg-AmCfCN3JkrYa3Q5z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA5MDA5MiBTYWx0ZWRfX5YEwEBLzlveS nfzpmQ9fJbWRGyIiKbvWaiUr2zjVidWPiYbOH2BE2Ewd5TzELey9Q2bl3XH8qHN4rtum27SGaBZ 17xW7LSNaVe7g1TLRkmwbUOBpkwzGzNU6ZK96x+anCttg6VIt+r+Ypr+a8/npUMnrE5heIF5shk KmhTvD8U/Ky4vfoIQIIgsDMiDnwu2uxdvBXTE2Wa2dqJooDN1iJmar3BVISzGCX1T8pHW+efuDx Kv35l8KVcXoI6B8y1pb8/qValYELU17agKof8S231RNbsAKvNwpnHDgmvECg1xDqB56Zjt8aHgZ HWNzQyq+YVkZoszGh+98Io3JdLbHBHG0qDss1MQ0D5RP/KeX7Jbf4HDXCmRaEczHxQqg5SN82FD HVZkm3t4sBYsxunozj0rvRWQkqmNfHc3MSgNp2DPdiH9ZpZR9/SXs/aDiPkZMCGoIYsYeOgk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-09_05,2025-06-05_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506090092 From: Abhinav Kumar dp_display caches the current display mode and then passes it onto the panel to be used for programming the panel params. Remove this two level passing and directly populated the panel's dp_display_mode instead. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 76 ++++++++++++++----------------------- 1 file changed, 29 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 4a9b65647cdef1ed6c3bb851f93df0db8be977af..9d2db9cbd2552470a36a63f70f517c35436f7280 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -92,7 +92,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; /* wait for audio signaling */ @@ -806,16 +805,29 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { - struct msm_dp_display_private *dp; + u32 bpp; - dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp = msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp = msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp = bpp; + + msm_dp_panel->msm_dp_mode.v_active_low = + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low = + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 = + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mode) && + msm_dp_panel->vsc_sdp_supported; - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp = mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + msm_dp_panel_init_panel_info(msm_dp_panel); return 0; } @@ -1431,10 +1443,13 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *msm_dp_display, bool msm_dp_wide_bus_available(const struct msm_dp *msm_dp_display) { struct msm_dp_display_private *dp; + struct msm_dp_panel *dp_panel; dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + dp_panel = dp->panel; + + if (dp_panel->msm_dp_mode.out_fmt_is_yuv_420) return false; return dp->wide_bus_supported; @@ -1496,10 +1511,6 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, bool force_link_train = false; msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); - return; - } if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display, 0); @@ -1517,15 +1528,6 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, return; } - rc = msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); - if (rc) { - DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); - mutex_unlock(&msm_dp_display->event_mutex); - return; - } - - hpd_state = msm_dp_display->hpd_state; - if (hpd_state == ST_CONNECTED && !dp->power_on) { msm_dp_display_host_phy_init(msm_dp_display); force_link_train = true; @@ -1604,33 +1606,13 @@ void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); msm_dp_panel = msm_dp_display->panel; - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mode)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp = msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel = 3 */ - msm_dp_display->msm_dp_mode.bpp = dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp = 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low = - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low = - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); - - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 = - drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && - msm_dp_panel->vsc_sdp_supported; + msm_dp_display_set_mode(dp, adjusted_mode, msm_dp_panel); /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en = - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display->wide_bus_supported; - msm_dp_display->catalog->wide_bus_en = - msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display->wide_bus_supported; + msm_dp_display->ctrl->wide_bus_en = msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? + false : msm_dp_display->wide_bus_supported; + msm_dp_display->catalog->wide_bus_en = msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? + false : msm_dp_display->wide_bus_supported; } void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) -- 2.34.1