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Mon, 9 Jun 2025 07:59:42 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , , , , Leon Romanovsky , Simon Horman , Richard Cochran , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , , , , , Dragos Tatulea , Cosmin Ratiu , Mark Bloch Subject: [PATCH net-next v3 09/12] net/mlx5e: Add support for UNREADABLE netmem page pools Date: Mon, 9 Jun 2025 17:58:30 +0300 Message-ID: <20250609145833.990793-10-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250609145833.990793-1-mbloch@nvidia.com> References: <20250609145833.990793-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1A:EE_|CYYPR12MB8869:EE_ X-MS-Office365-Filtering-Correlation-Id: 5949e366-a580-42ae-ff70-08dda76650f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YTDo5QvDfChh+ePtw0eALMemJyOo+5n4+PYDWSL5l1r/0wlKHiU8g404McQU?= =?us-ascii?Q?ZsfCAuk43kXDEd19C61Vv4OxL8SX2dCnOgm3MVTQ8oz7cHNhqqnT+2rzgw7r?= =?us-ascii?Q?f0378gbfnnHdWJe+JWO98j+cCrs7f7SzYD0QlJQgr8NL8bzcvDOtnANrOxun?= =?us-ascii?Q?PdGWWCgBSqb6MllgwCRfnaBlt0tRP2mQ7kNKfRNQNdWWcT+/MezVPp8AhSaL?= =?us-ascii?Q?f4qWLAfOCy+ufmF+skSeHe6CIsmHX0Iayf/kEgZAJ1rNVCh2Z2AqKG5Pkhwa?= =?us-ascii?Q?E42gLy2xOF+1GjPxsdrQyoENE1MDicuu5348LXaBwbaZgbqLnuW0/zBjiOyG?= =?us-ascii?Q?evI8BMMeSeQI3X74SU/+2L1kttJWUU/t0ff3MCpmcUDDgkJCeMAcpA3JkVSN?= =?us-ascii?Q?jVstYMEMKzOBHOAUFHlN7G1ry/w98/PmJoVESvRowIYXglugljjgYnHuncLp?= =?us-ascii?Q?7DH0lVGHlzp7rAzlnXW9a5pOdTbT5knzGh08DC+BxfQN5aXCWCg7Lp2+3oiX?= =?us-ascii?Q?G1mMwNLOiJnuxiSlox4i7nfGnNOiH5froyEz5eadtWY86inTmL5IAAOQ6f9Y?= =?us-ascii?Q?y8znTWqJY+efFOKKdGZU0UU1O0s9stxVGwfEX5okrXhYQ8DxoPNNJrlof0l0?= =?us-ascii?Q?4YRIJKxqRf6EitHsOFAlNcxDzYijErTw19QgK+k3inOUxePWfDRVqs++zDM0?= =?us-ascii?Q?JZo67GsSQZSsJJSKuiAKlDD3UXdr90lSMiL2oo/OkBkIhOuCbE1dQwJW9neE?= =?us-ascii?Q?lSPhDtxn61Aq/SZuGBLmFMe7BApxmVCsZ2uJzA95NYFZM+391XolJ3jJNk0E?= =?us-ascii?Q?tN012BLmwPOHKx/OyJ6ldMCu6BpRut7NtHijQ9ViUCwD45dBNmvuNV1KzWcR?= =?us-ascii?Q?6YnDBNezUP6B4vr814MaFQNnIcFhxdy+oMZwt2ogu7qTYZ7HkLFeFmC7djf2?= =?us-ascii?Q?oBYBs0QZwOuY47CE7q/K4o++T1uMochzH6KwcooMvHaFDtErK1p9THsQL/SP?= =?us-ascii?Q?XatPweUQ4EIgqBVpn/1Vln9Y1xmrTKIvcKLOD+4hvEbRvqlYGHmkFMBjtVOw?= =?us-ascii?Q?+h+zaVzKWw68+O9VdOKNjhyHNiweJp0sjPgULqmPxbPSLaR3oreFCnxYe6PZ?= =?us-ascii?Q?P6V1Ap1RuTKCWD+ihF2FczHwoRzscNHYnaA3yeT+kG4o1oAvXfrfAUlyp8Wb?= =?us-ascii?Q?cvoWrSaDYIVrkg/523r7hOgDDYIKQs1Nii2fHIINGYxMxnFU+m63ak3SOvq2?= =?us-ascii?Q?WQqKAKAvDfk7ZFoW5LaI2EnSwsDftAhmB5euBdG+w1XnNNeu11786PiRUath?= =?us-ascii?Q?Ol5Mb8FwzSsYzN7xkfDV0iQHShsjqWxv3KJMqbHbRDUnvuqZD2bk/iP3FZIK?= =?us-ascii?Q?TEuigcJXUsi2WsnmS13kOIOyZaA4cnHFstS/UYI/j9EzPvXDLxqtFWshTNIE?= =?us-ascii?Q?ZsMHXMF3t6zdJVcV+2oxFIz6DvLuWRQ7DEQ8QK7YtSYgYJZhQenqNECiHiOJ?= =?us-ascii?Q?xxVKLWNbT50Hlzs1MpH/5OwybDDBtM0P7+Ro?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2025 15:00:04.1900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5949e366-a580-42ae-ff70-08dda76650f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8869 From: Saeed Mahameed On netdev_rx_queue_restart, a special type of page pool maybe expected. In this patch declare support for UNREADABLE netmem iov pages in the pool params only when header data split shampo RQ mode is enabled, also set the queue index in the page pool params struct. Shampo mode requirement: Without header split rx needs to peek at the data, we can't do UNREADABLE_NETMEM. The patch also enables the use of a separate page pool for headers when a memory provider is installed for the queue, otherwise the same common page pool continues to be used. Signed-off-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 5e649705e35f..a51e204bd364 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -749,7 +749,9 @@ static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) static bool mlx5_rq_needs_separate_hd_pool(struct mlx5e_rq *rq) { - return false; + struct netdev_rx_queue *rxq = __netif_get_rx_queue(rq->netdev, rq->ix); + + return !!rxq->mp_params.mp_ops; } static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, @@ -964,6 +966,11 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, pp_params.netdev = rq->netdev; pp_params.dma_dir = rq->buff.map_dir; pp_params.max_len = PAGE_SIZE; + pp_params.queue_idx = rq->ix; + + /* Shampo header data split allow for unreadable netmem */ + if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) + pp_params.flags |= PP_FLAG_ALLOW_UNREADABLE_NETMEM; /* page_pool can be used even when there is no rq->xdp_prog, * given page_pool does not handle DMA mapping there is no -- 2.34.1