From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C082E645; Tue, 10 Jun 2025 01:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749518659; cv=none; b=J3Trt3yB3s5miorAAFrGwsCii8T44tNouQSWoiEt9sNdBEm1NkrlAh2UdyS+jM6hmHxrVBjpfzSmZcHFlDuVYuzeCx6YlwPkRMUKRjPKgiJrkXFfHWUmp3i6XX9AFzXeuKt520VJLFP4xI9/Ms2Fp5/RVh351+2+2Sb80xInVFo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749518659; c=relaxed/simple; bh=jaPwOsygIgo+0p42l+vQGQxj45Vn9tNHEkFW/45Xgh4=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=dbiANmh0OLjkGOAM9ro5WV+mTCpVlIv6uI5slea3IdC/Oyyl3/eWYi4BkFqHr1Fcwnt5pRIsTPDVCdI+acZFVsJmbkfmdQIHazZmGvduckuU1+xIxRKAQfRtRq7r4IYi7aAnRT2zc1RR3F0BSt9DMjJ/LBzmyP5FP9VKdbFwstM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 10 Jun 2025 09:24:06 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 10 Jun 2025 09:24:06 +0800 From: Jacky Chou To: , , , CC: , , , , , , , , , , , , , , , Subject: [net-next v2 0/4] net: ftgmac100: Add SoC reset support for RMII mode Date: Tue, 10 Jun 2025 09:24:02 +0800 Message-ID: <20250610012406.3703769-1-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This patch series adds support for an optional reset line to the ftgmac100 ethernet controller, as used on Aspeed SoCs. On these SoCs, the internal MAC reset is not sufficient to reset the RMII interface. By providing a SoC-level reset via the device tree "resets" property, the driver can properly reset both the MAC and RMII logic, ensuring correct operation in RMII mode. The series includes: - Device tree binding update to document the new "resets" property. - Addition of MAC1 and MAC2 reset definitions for AST2600. - Device tree changes for AST2600 to use the new reset properties. - Driver changes to assert/deassert the reset line as needed. This improves reliability and initialization of the MAC in RMII mode on Aspeed platforms. Jacky Chou (4): dt-bindings: net: ftgmac100: Add resets property dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2 ARM: dts: aspeed-g6: Add resets property for MAC controllers net: ftgmac100: Add optional reset control for RMII mode on Aspeed SoCs .../bindings/net/faraday,ftgmac100.yaml | 19 ++++++++++++++ arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 +++ drivers/net/ethernet/faraday/ftgmac100.c | 26 +++++++++++++++++++ include/dt-bindings/clock/ast2600-clock.h | 2 ++ 4 files changed, 51 insertions(+) --- v2: - Added restriction on resets property in faraday,ftgmac100.yaml. --- -- 2.34.1