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X-OriginatorOrg: topic.nl X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2025 14:39:30.4069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a758b62e-7a97-492c-24a5-08dda82c9bec X-MS-Exchange-CrossTenant-Id: 449607a5-3517-482d-8d16-41dd868cbda3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=449607a5-3517-482d-8d16-41dd868cbda3;Ip=[13.93.42.39];Helo=[westeu12-emailsignatures-cloud.codetwo.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A6.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7897 When the driver loads, the transceiver and endpoint may still be setting up a link. Wait for that to complete before continuing. This fixes that the PCIe core does not work when loading the PL bitstream from userspace. Existing reference designs worked because the endpoint and PL were initialized by a bootloader. If the endpoint power and/or reset is supplied by the kernel, or if the PL is programmed from within the kernel, the link won't be up yet and the driver just has to wait for link training to finish. As the PCIe spec allows up to 100 ms time to establish a link, we'll allow up to 200ms before giving up. Signed-off-by: Mike Looijmans --- Changes in v4: Adapt patch description to "PCI: xilinx:" format Explain the initialization order issue better Use PCIE_T_RRS_READY_MS instead of 100ms Changes in v2: Split into "reset GPIO" and "wait for link" patches Add timeout explanation drivers/pci/controller/pcie-xilinx.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/= pcie-xilinx.c index e36aa874bae9..e8a07535539e 100644 --- a/drivers/pci/controller/pcie-xilinx.c +++ b/drivers/pci/controller/pcie-xilinx.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -126,6 +127,19 @@ static inline bool xilinx_pcie_link_up(struct xilinx_p= cie *pcie) XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0; } =20 +static int xilinx_pci_wait_link_up(struct xilinx_pcie *pcie) +{ + u32 val; + + /* + * PCIe r6.0, sec 6.6.1 provides 100ms timeout. Since this is FPGA + * fabric, we're more lenient and allow 200 ms for link training. + */ + return readl_poll_timeout(pcie->reg_base + XILINX_PCIE_REG_PSCR, val, + (val & XILINX_PCIE_REG_PSCR_LNKUP), 2 * USEC_PER_MSEC, + 2 * PCIE_T_RRS_READY_MS * USEC_PER_MSEC); +} + /** * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts * @pcie: PCIe port information @@ -492,7 +506,7 @@ static void xilinx_pcie_init_port(struct xilinx_pcie *p= cie) { struct device *dev =3D pcie->dev; =20 - if (xilinx_pcie_link_up(pcie)) + if (!xilinx_pci_wait_link_up(pcie)) dev_info(dev, "PCIe Link is UP\n"); else dev_info(dev, "PCIe Link is DOWN\n"); --=20 2.43.0 base-commit: f09079bd04a924c72d555cd97942d5f8d7eca98c branch: linux-master-pci-reset Met vriendelijke groet / kind regards,=0A= =0A= Mike Looijmans=0A= System Expert=0A= =0A= =0A= TOPIC Embedded Products B.V.=0A= Materiaalweg 4, 5681 RJ Best=0A= The Netherlands=0A= =0A= T: +31 (0) 499 33 69 69=0A= E: mike.looijmans@topic.nl=0A= W: www.topic.nl=0A= =0A= Please consider the environment before printing this e-mail=0A=