[PATCH v3 00/44] x86: Introduce a centralized CPUID data model

[PATCH v3 00/44] x86: Introduce a centralized CPUID data model

[Ahmed S. Darwish]

Hi,

This series introduces a centralized CPUID model for the x86 subsystem.

Rationale for this work can be found at:

    https://lore.kernel.org/lkml/874ixernra.ffs@tglx

    https://gitlab.com/x86-cpuid.org/x86-cpuid-db

The first 19 patches can be independently applied.


Changelog v3
~~~~~~~~~~~~

* Transform the final CPUID(0x80000006) call site, inline C function
  cpuid_amd_hygon_has_l3_cache() at <asm/cpuid/api.h>, to the new parsed
  CPUID API.

  Due to this C inline function requiring access to 'struct cpuinfo_x86',
  a circular dependency emerged in the headers:

  <asm/cpuid/api.h>    includes    <asm/processor.h>	# for 'struct cpuinfo_x86'
  <asm/processor.h>    includes    <asm/cpuid/api.h>	# for CPUID types

  Turns out, <asm/processor.h> does not need <asm/cpuid/api.h>, and
  <asm/cpuid/types.h> is enough for it.

  Thus, let <asm/processor.h> include <asm/cpuid/types.h> instead.

  For all call sites that included the CPUID API header implicitly
  through <asm/processor.h>, transform them to explicitly include
  <asm/cpuid/api.h> instead.

  This <asm/processor.h>⇔CPUID-API headers disentanglement is done by
  patches 1=>19.

* Initially (at v1, v2), there were two CPUID parser functions to fill a
  CPUID table: cpuid_parser_scan_cpu() and cpuid_parser_rescan_cpu().
  The latter zeroed-out the CPUID table beforehand, while the former did
  not.

  For v3, let the CPUID parser provide only one function where the CPUID
  table is always zeroed beforehand: cpuid_parser_scan_cpu(),

  Rationale for this decision is explained at patch 21/44 ("x86/cpuid:
  Introduce a centralized CPUID parser"), inside
  cpuid_parser_scan_cpu()'s implementation.

* Minimize the code for leaf-specific CPUID parser code by removing some
  redundant steps: remove initial zeroing of "output->info->nr_entries",
  remove a static assert, etc.

* Drop the v2 patch, ("x86/cpuid: Warn once on invalid CPUID(0x2)
  iteration count"), from this model v3.  On AMD machines with zeroed
  CPUID(0x2) output, a false warning will be triggered.

  This is because the CPUID model generic leaves parser has no vendor
  filtering so far; i.e. all CPUID leaves are queried on all CPU vendors.
  This keeps the parser simple, but I'll think a bit if adding minimal
  vendor filtering will be useful for this PQ's next iteration.

* Apply more CPUID parser code readability enhancements.

* Series is on top of v6.16-rc1.


Changelog v2
~~~~~~~~~~~~

( [PATCH v2 00/27] x86: Introduce a centralized CPUID data model
  https://lore.kernel.org/x86-cpuid/20250605192356.82250-1-darwi@linutronix.de )

* Pre-requisite CPUID headers cleanups, requested by Ingo, are now merged:

    [PATCH v1 0/9] x86/cpuid: Headers cleanup
    https://lore.kernel.org/lkml/20250508150240.172915-1-darwi@linutronix.de

    [PATCH v2 0/2] x86/cpuid: Headers cleanup
    https://lore.kernel.org/lkml/20250515202143.34448-1-darwi@linutronix.de

  This v2 series is rebased on top of the above restructuring, where the
  CPUID headers become:

    include/asm/cpuid/
    ├── api.h
    ├── leaf_types.h		// x86-cpuid-db auto-generated file
    └── types.h

* At <asm/cpuid/api.h>, add a clear rational for call sites to use the
  new API:

   /*
    * External APIs for accessing parsed CPUID data:
    *
    * Call sites should use below APIs instead of invoking direct CPUID
    * queries.  Benefits include:
    *
    * - Return CPUID output as typed C structures that are auto-generated
    *   from a centralized database (see <cpuid/leaf_types.h).  Such data
    *   types have a full C99 bitfield layout per CPUID leaf/subleaf
    *   combination.  Call sites can thus avoid doing ugly and cryptic
    *   bitwise operations on raw CPUID data.
    *
    * - Return cached, per-CPU, CPUID output.  Below APIs do not invoke
    *   any CPUID queries, thus avoiding their side effects like
    *   serialization and VM exits.  Call-site-specific hard coded
    *   constants and macros for caching CPUID query outputs can also be
    *   avoided.
    *
    * - Return sanitized CPUID data.  Below APIs return NULL if the given
    *   CPUID leaf/subleaf input is not supported by hardware, or if the
    *   hardware CPUID output was deemed invalid by the CPUID parser.
    *   This centralizes all CPUID data sanitization in one place (the
    *   kernel's CPUID parser.)
    *
    * - A centralized global view of system CPUID data.  Below APIs will
    *   reflect any kernel-enforced feature masking or overrides, unlike
    *   ad hoc parsing of raw CPUID output by drivers and individual call
    *   sites.
    */

* Since this model's APIs will be the official kernel CPUID API, free the
  cpuid_subleaf() and cpuid_leaf() namespace and dedicate it to the model:

    patch 02/27 ("x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs")

  After some local iterative work, I've found below API names to make the
  most sense.  They look "so obvious" now, which is IMHO a good sign.
  The CPUID model APIs become:

    /*
     * For CPUID leaves with static, compile-time, subleaves
     */

    cpuid_subleaf(_cpuinfo, _leaf, _subleaf)
    cpuid_leaf(_cpuinfo, _leaf)
    cpuid_leaf_regs(_cpuinfo, _leaf)

    /*
     * For CPUID leaves with dynamic subleaves
     */

    cpuid_subleaf_index(_cpuinfo, _leaf, _idx)
    cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx)
    cpuid_subleaf_count(_cpuinfo, _leaf)

  The difference between the static and dynamic parts of the API is
  described in detail at patch 04/27 ("x86/cpuid: Introduce a centralized
  CPUID data model").

  In general, all of the above APIs translate to a /single/ assembly
  instruction offset calculation.  For example:

    const struct leaf_0x7_0 *l7_0;
    const struct leaf_0x7_1 *l7_1;

    l7_0 = cpuid_subleaf(c, 0x7, 0);
                         |   |   └────────┐
                         |   └─────────┐  |
                         *             *  *
                        &c.cpuid.leaf_0x7_0[0]

    l7_1 = cpuid_subleaf(c, 0x7, 1);
                         |   |   └────────┐
                         |   └─────────┐  |
                         *             *  *
                        &c.cpuid.leaf_0x7_1[0]

* Per Ingo's feedback, avoid the "CPUID scanner" terminology and
  standardize on "CPUID parser".  Use the new terminology for all of the
  relevent data structures, functions, and file names: "cpuid_parser.h",
  cpuid_parser.c, 'struct cpuid_parse_entry', cpuid_parser_scan_cpu(),
  cpuid_parser_rescan_cpu(), etc.

* Standardize on "__cpuid_leaves_" and "__cpuid_table_" prefixes for all
  of the <cpuid/api.h> macros that are intended for internal CPUID usage.

* Apply multiple code clarity enhancements to the CPUID parser.  No
  change in functionality.

* For the series main patch, 04/27 ("x86/cpuid: Introduce a centralized
  CPUID data model"), expand it with full design and implementation
  details rational.

* Per Sohil's feedback, apply output formatting enhancements to the new
  CPUID debugfs files x86/cpuid/[0-ncpu]:

    patch 07/27 ("x86/cpuid: Introduce CPUID parser debugfs interface")

* Per Ingo's feedback, (lightly) log the cases where the CPUID parser
  encounters bogus hardware CPUID data:

    patch 13/27 ("x86/cpuid: Warn once on invalid CPUID(0x2) iteration count")

* Per Ingo's feedback, break CPUID(0x4) call-site patch into:

    patch 19/27 ("x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code")
    patch 20/27 ("x86/cacheinfo: Use parsed CPUID(0x4)")

* Enhance all of the project's APIs kernel-doc.

* Massage all commit logs and code comments for overall clarity.


Changelog v1
~~~~~~~~~~~~

( [PATCH v1 00/26] x86: Introduce centralized CPUID model
  https://lore.kernel.org/lkml/20250506050437.10264-1-darwi@linutronix.de )

This series introduces a CPUID model for the x86 subsystem.

It is based on top of the CPUID refactorings and bugfixes currently
merged at tip:x86/cpu:

    [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings
    https://lore.kernel.org/lkml/20250304085152.51092-1-darwi@linutronix.de

    [PATCH v4 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings
    https://lore.kernel.org/lkml/20250324133324.23458-1-darwi@linutronix.de

    [PATCH v2 0/2] x86/cacheinfo: Fixes for CPUID(0x80000005) and CPUID(0x80000006)
    https://lore.kernel.org/lkml/20250409122233.1058601-1-darwi@linutronix.de

    [PATCH v1 0/2] x86: CPUID refactorings: follow-up
    https://lore.kernel.org/lkml/20250411070401.1358760-1-darwi@linutronix.de

    [PATCH v3 00/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.3
    https://lore.kernel.org/lkml/20250324142042.29010-1-darwi@linutronix.de

First, deploy <asm/cpuid/leaves.h>, as generated by x86-cpuid-db. [*]

The header is in the form:

    /* SPDX-License-Identifier: MIT */
    /* Generator: x86-cpuid-db v2.4 */

    /*
     * Leaf 0x0
     * Maximum standard leaf number + CPU vendor string
     */

    struct leaf_0x0_0 {
     	u32	max_std_leaf		: 32; // Highest standard CPUID leaf supported
     	u32	cpu_vendorid_0		: 32; // CPU vendor ID string bytes 0 - 3
     	u32	cpu_vendorid_2		: 32; // CPU vendor ID string bytes 8 - 11
     	u32	cpu_vendorid_1		: 32; // CPU vendor ID string bytes 4 - 7
    };

    /*
     * Leaf 0x1
     * CPU FMS (Family/Model/Stepping) + standard feature flags
     */

    struct leaf_0x1_0 {
	// eax
	u32	stepping		:  4, // Stepping ID
		base_model		:  4, // Base CPU model ID
		base_family_id		:  4, // Base CPU family ID
		...;
	// ebx
	u32	brand_id		:  8, // Brand index
		clflush_size		:  8, // CLFLUSH instruction cache line size
		n_logical_cpu		:  8, // Logical CPU count
		local_apic_id		:  8; // Initial local APIC physical ID
	// ecx
	...
    };

    ...

where for each 'struct leaf_0xN_M', N is the leaf number and M is the
subleaf.  The bitfields mirror the x86-cpuid-db kcpuid auto-generated
file, as already merged mainline at tools/arch/x86/kcpuid/cpuid.csv.

Create a 'struct cpuid_leaves' in <cpuid/types.h> to hold scanned CPUID
data:

    struct cpuid_leaves {
     	struct leaf_0x0_0	leaf_0x0_0[1];
     	struct leaf_query_info	leaf_0x0_0_info;

     	struct leaf_0x1_0	leaf_0x1_0[1];
     	struct leaf_query_info	leaf_0x0_0_info;

     	struct leaf_0x4_0	leaf_0x4_0[8];
     	struct leaf_query_info	leaf_0x4_0_info;
     	...
    };

where the 'struct leaf_0xN_M' definitions are auto-generated.  Use arrays
to handle CPUID leaves with uniform subleaf structures, which is typical
for enumerating hierarchical objects; e.g., CPUID(0x4) cache topology
enumeration, CPUID(0xd) XSAVE enumeration, CPUID(0x12) SGX enclaves
enumeration, and CPUID(0x8000001d) AMD cache enumeration.

For each entry in the CPUID table, associate a 'struct leaf_query_info'.
It is to be filled for each available CPUID leaf by the generic CPUID
scanning logic.

Define a 'struct cpuid_table' for caching each CPU's CPUID table, and
embed in it a 'struct cpuid_leaves' instance.  This way, global table
data can also be added.  Embed an instance of 'struct cpuid_table' in the
'struct cpuinfo_x86' CPU capability structure(s):

    struct cpuinfo_x86 {
     	...
     	struct cpuid_table	cpuid_table;
     	...
    };

This way, centralized CPUID data can be accessed on early boot using
'boot_cpu_data', and later on a per-CPU basis using the 'cpu_info'
per-CPU CPU capability structures.

Build the CPUID data in that "struct leaf_0xN_M leaf_0xN_M" format to
facilitate direct CPUID table and CPUID bitfields access.  Accessing
scanned CPUID bitfields can be done using statements like:

    u32 level = cpudata_cpuid(c, 0x0)->max_std_leaf;

    const struct leaf_0x1_0 *l1 = cpudata_cpuid(c, 0x1);
    c->x86_stepping		= l1->stepping;
    c->x86_clflush_size		= l1->clflush_size * 8;

    const struct leaf_0x80000005_0 *el5 = cpudata_cpuid(c, 0x80000005);
    unsigned assoc		= el5->l1_dcache_assoc;
    unsigned line_size		= el5->l1_dcache_line_size;

    unsigned l1d_index = 0;	// CPUID(0x4) subleaf 0: L1 data cache
    unsigned l1i_index = 1;	// CPUID(0x4) subleaf 1: L1 inst cache
    const struct leaf_0x4_0 *l1d = cpudata_cpuid_index(0x4, l1d_index);
    const struct leaf_0x4_0 *l1i = cpudata_cpuid_index(0x4, l1i_index);

    /* Then access l1d->cache_nways, l1d->cache_nsets, ... */

where in the above snippet, 'c' is the CPU's capability structure.
Define all macros at <cpuid/table_api.h>, and add proper kernel docs.

Beside the model's centralization benefits, this also avoids using the
ugly manual bit-fiddling common in a lot of CPUID call sites.  The late
part of this PQ clearly shows this.  As a start, switch the following
leaves to scanned CPUID access:

    CPUID(0x0)
    CPUID(0x1)
    CPUID(0x2)
    CPUID(0x4)
    CPUID(0x80000000)
    CPUID(0x80000005)
    CPUID(0x80000006)
    CPUID(0x8000001d)

With these converted, the entirety of the x86/cacheinfo code is void of
any direct CPUID queries.

Introduce the debugfs files 'x86/scanned_cpuid/[0-ncpus]' to dump the
cached CPUID table for each CPU.  This should help with tricky bug
reports in the future, if/when the scanned CPUID tables get
(unexpectedly) out of sync with actual hardware state.  Example output
from an Intel Core i5-8250U laptop:

   $ cat /sys/kernel/debug/x86/scanned_cpuid/cpus/1

    Leaf 0x00000000, subleaf 0:
    cached: EAX=0x00000016	EBX=0x756e6547	ECX=0x6c65746e	EDX=0x49656e69
    actual: EAX=0x00000016	EBX=0x756e6547	ECX=0x6c65746e	EDX=0x49656e69

    Leaf 0x00000001, subleaf 0:
    cached: EAX=0x000806ea	EBX=0x02100800	ECX=0x7ffafbbf	EDX=0xbfebfbff
    actual: EAX=0x000806ea	EBX=0x02100800	ECX=0x7ffafbbf	EDX=0xbfebfbff

    ...

Thanks!

8<-----

Ahmed S. Darwish (44):
  x86/cpuid: Remove transitional <asm/cpuid.h> header
  ASoC: Intel: avs: Include CPUID header at file scope
  x86/boot: Reorder sme.c headers alphabetically
  x86/cpu: Reorder scattered.c headers alphabetically
  x86/cpu/amd: Reorder headers alphabetically
  x86/cpu/topology: Reorder headers alphabetically
  x86/mce: Reorder core.c headers alphabetically
  x86/paravirt: Reorder headers alphabetically
  x86/perf/zhaoxin: Reorder headers alphabetically
  x86/resctrl: Reorder core.c headers alphabetically
  x86/tdx: Reorder headers alphabetically
  cpufreq: Reorder headers alphabetically
  hwmon: (fam15h_power) Reorder headers alphabetically
  hwmon: (k8temp) Reorder headers alphabetically
  perf/x86/amd/uncore: Reorder headers alphabetically
  thermal: intel: Reorder headers alphabetically
  treewide: Explicitly include <asm/cpuid/api.h>
  x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs
  x86/cpuid: Introduce <asm/cpuid/leaf_types.h>
  x86/cpuid: Introduce a centralized CPUID data model
  x86/cpuid: Introduce a centralized CPUID parser
  x86/cpuid: Parse CPUID(0x80000000)
  x86/cpuid: Introduce CPUID parser debugfs interface
  x86/cpu: Use parsed CPUID(0x0)
  x86/cpu: Use parsed CPUID(0x80000000)
  x86/lib: Add CPUID(0x1) CPU family and model calculation
  x86/cpu: Use parsed CPUID(0x1)
  x86/cpuid: Parse CPUID(0x2)
  x86/cpuid: Introduce parsed CPUID(0x2) API
  x86/cpu: Use parsed CPUID(0x2)
  x86/cacheinfo: Use parsed CPUID(0x2)
  x86/cpuid: Remove direct CPUID(0x2) query API
  x86/cpuid: Parse deterministic cache parameters CPUID leaves
  x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code
  x86/cacheinfo: Use parsed CPUID(0x4)
  x86/cacheinfo: Use parsed CPUID(0x8000001d)
  x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006)
  x86/cacheinfo: Use auto-generated data types
  x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
  x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference
  x86/cpu: <asm/processor.h>: Do not include CPUID API header
  x86/cpuid: Use parsed CPUID(0x80000006)
  x86/cpu: Rescan CPUID table after PSN disable
  x86/cpu: Rescan CPUID table after unlocking full CPUID range

 MAINTAINERS                                  |    1 +
 arch/x86/boot/compressed/pgtable_64.c        |    1 +
 arch/x86/boot/startup/sme.c                  |    9 +-
 arch/x86/coco/tdx/tdx.c                      |    6 +-
 arch/x86/events/amd/core.c                   |    2 +
 arch/x86/events/amd/ibs.c                    |    1 +
 arch/x86/events/amd/lbr.c                    |    2 +
 arch/x86/events/amd/power.c                  |    3 +
 arch/x86/events/amd/uncore.c                 |   15 +-
 arch/x86/events/intel/core.c                 |    1 +
 arch/x86/events/intel/lbr.c                  |    1 +
 arch/x86/events/zhaoxin/core.c               |   12 +-
 arch/x86/include/asm/acrn.h                  |    2 +
 arch/x86/include/asm/cpu.h                   |    6 +
 arch/x86/include/asm/cpuid.h                 |    8 -
 arch/x86/include/asm/cpuid/api.h             |  321 ++-
 arch/x86/include/asm/cpuid/leaf_types.h      | 2055 ++++++++++++++++++
 arch/x86/include/asm/cpuid/types.h           |  117 +
 arch/x86/include/asm/microcode.h             |    1 +
 arch/x86/include/asm/processor.h             |    3 +-
 arch/x86/include/asm/xen/hypervisor.h        |    1 +
 arch/x86/kernel/amd_nb.c                     |    9 +-
 arch/x86/kernel/cpu/Makefile                 |    3 +-
 arch/x86/kernel/cpu/amd.c                    |   21 +-
 arch/x86/kernel/cpu/cacheinfo.c              |  284 +--
 arch/x86/kernel/cpu/centaur.c                |    1 +
 arch/x86/kernel/cpu/common.c                 |   58 +-
 arch/x86/kernel/cpu/cpuid_debugfs.c          |  102 +
 arch/x86/kernel/cpu/cpuid_parser.c           |  201 ++
 arch/x86/kernel/cpu/cpuid_parser.h           |  109 +
 arch/x86/kernel/cpu/hygon.c                  |    1 +
 arch/x86/kernel/cpu/intel.c                  |   17 +-
 arch/x86/kernel/cpu/mce/core.c               |   63 +-
 arch/x86/kernel/cpu/mce/inject.c             |    1 +
 arch/x86/kernel/cpu/resctrl/core.c           |    6 +-
 arch/x86/kernel/cpu/resctrl/monitor.c        |    1 +
 arch/x86/kernel/cpu/scattered.c              |    3 +-
 arch/x86/kernel/cpu/sgx/main.c               |    3 +
 arch/x86/kernel/cpu/topology_amd.c           |    3 +-
 arch/x86/kernel/cpu/topology_common.c        |    3 +-
 arch/x86/kernel/cpu/topology_ext.c           |    3 +-
 arch/x86/kernel/cpu/transmeta.c              |    3 +
 arch/x86/kernel/cpu/zhaoxin.c                |    1 +
 arch/x86/kernel/cpuid.c                      |    6 +-
 arch/x86/kernel/paravirt.c                   |   29 +-
 arch/x86/kvm/cpuid.h                         |    3 +
 arch/x86/kvm/mmu/spte.c                      |    1 +
 arch/x86/lib/cpu.c                           |   41 +-
 drivers/cpufreq/speedstep-lib.c              |    6 +-
 drivers/firmware/efi/libstub/x86-5lvl.c      |    1 +
 drivers/hwmon/fam15h_power.c                 |   14 +-
 drivers/hwmon/k10temp.c                      |    2 +
 drivers/hwmon/k8temp.c                       |   12 +-
 drivers/thermal/intel/intel_hfi.c            |    1 +
 drivers/thermal/intel/x86_pkg_temp_thermal.c |   15 +-
 sound/soc/intel/avs/tgl.c                    |   25 +-
 56 files changed, 3215 insertions(+), 405 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h
 create mode 100644 arch/x86/include/asm/cpuid/leaf_types.h
 create mode 100644 arch/x86/kernel/cpu/cpuid_debugfs.c
 create mode 100644 arch/x86/kernel/cpu/cpuid_parser.c
 create mode 100644 arch/x86/kernel/cpu/cpuid_parser.h

base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
-- 
2.49.0

[PATCH v3 01/44] x86/cpuid: Remove transitional <asm/cpuid.h> header

[Ahmed S. Darwish]

All CPUID call sites were updated at commit:

    968e30006807 ("x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header")

to include <asm/cpuid/api.h> instead of <asm/cpuid.h>.

The <asm/cpuid.h> header was still retained as a wrapper, just in case
some new code in -next started using it.  Now that everything is merged
to Linus' tree, remove the header.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid.h | 8 --------
 1 file changed, 8 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h

diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
deleted file mode 100644
index d5749b25fa10..000000000000
--- a/arch/x86/include/asm/cpuid.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_X86_CPUID_H
-#define _ASM_X86_CPUID_H
-
-#include <asm/cpuid/api.h>
-
-#endif /* _ASM_X86_CPUID_H */
-- 
2.49.0

[PATCH v3 02/44] ASoC: Intel: avs: Include CPUID header at file scope

[Ahmed S. Darwish]

Commit

    cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platforms")

includes the main CPUID header from within a C function.  This obviously
works by luck and forbids valid refactorings inside the CPUID header.

Include the CPUID header at file scope instead.

Note, for the CPUID(0x15) leaf number, use CPUID_LEAF_TSC instead of
defining a custom local macro for it.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 sound/soc/intel/avs/tgl.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c
index 9dbb3ad0954a..cf19d3a7ced2 100644
--- a/sound/soc/intel/avs/tgl.c
+++ b/sound/soc/intel/avs/tgl.c
@@ -10,8 +10,6 @@
 #include "avs.h"
 #include "messages.h"
 
-#define CPUID_TSC_LEAF 0x15
-
 static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
 {
 	core_mask &= AVS_MAIN_CORE_MASK;
@@ -39,22 +37,31 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stal
 	return avs_dsp_core_stall(adev, core_mask, stall);
 }
 
+#ifdef CONFIG_X86
+#include <asm/cpuid/api.h>
+static unsigned int intel_crystal_freq_hz(void)
+{
+	return cpuid_ecx(CPUID_LEAF_TSC);
+}
+#else
+static unsigned int intel_crystal_freq_hz(void)
+{
+	return 0;
+}
+#endif /* !CONFIG_X86 */
+
 static int avs_tgl_config_basefw(struct avs_dev *adev)
 {
+	unsigned int freq = intel_crystal_freq_hz();
 	struct pci_dev *pci = adev->base.pci;
 	struct avs_bus_hwid hwid;
 	int ret;
-#ifdef CONFIG_X86
-	unsigned int ecx;
 
-#include <asm/cpuid/api.h>
-	ecx = cpuid_ecx(CPUID_TSC_LEAF);
-	if (ecx) {
-		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx);
+	if (freq) {
+		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(freq), &freq);
 		if (ret)
 			return AVS_IPC_RET(ret);
 	}
-#endif
 
 	hwid.device = pci->device;
 	hwid.subsystem = pci->subsystem_vendor | (pci->subsystem_device << 16);
-- 
2.49.0

[PATCH v3 03/44] x86/boot: Reorder sme.c headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/startup/sme.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c
index 70ea1748c0a7..922b236be02f 100644
--- a/arch/x86/boot/startup/sme.c
+++ b/arch/x86/boot/startup/sme.c
@@ -34,15 +34,15 @@
  */
 #define USE_EARLY_PGTABLE_L5
 
+#include <linux/cc_platform.h>
 #include <linux/kernel.h>
-#include <linux/mm.h>
 #include <linux/mem_encrypt.h>
-#include <linux/cc_platform.h>
+#include <linux/mm.h>
 
+#include <asm/coco.h>
 #include <asm/init.h>
-#include <asm/setup.h>
 #include <asm/sections.h>
-#include <asm/coco.h>
+#include <asm/setup.h>
 #include <asm/sev.h>
 
 #define PGD_FLAGS		_KERNPG_TABLE_NOENC
-- 
2.49.0

[PATCH v3 04/44] x86/cpu: Reorder scattered.c headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/scattered.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index dbf6d71bdf18..3d23b943f596 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -4,8 +4,8 @@
  */
 #include <linux/cpu.h>
 
-#include <asm/memtype.h>
 #include <asm/apic.h>
+#include <asm/memtype.h>
 #include <asm/processor.h>
 
 #include "cpu.h"
-- 
2.49.0

[PATCH v3 05/44] x86/cpu/amd: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/amd.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 93da466dfe2c..c988d876b700 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1,29 +1,29 @@
 // SPDX-License-Identifier: GPL-2.0-only
-#include <linux/export.h>
 #include <linux/bitops.h>
 #include <linux/elf.h>
-#include <linux/mm.h>
-
+#include <linux/export.h>
 #include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/random.h>
 #include <linux/sched.h>
 #include <linux/sched/clock.h>
-#include <linux/random.h>
 #include <linux/topology.h>
+
 #include <asm/amd/fch.h>
-#include <asm/processor.h>
 #include <asm/apic.h>
 #include <asm/cacheinfo.h>
 #include <asm/cpu.h>
 #include <asm/cpu_device_id.h>
-#include <asm/spec-ctrl.h>
-#include <asm/smp.h>
+#include <asm/debugreg.h>
+#include <asm/delay.h>
+#include <asm/msr.h>
 #include <asm/numa.h>
 #include <asm/pci-direct.h>
-#include <asm/delay.h>
-#include <asm/debugreg.h>
+#include <asm/processor.h>
 #include <asm/resctrl.h>
-#include <asm/msr.h>
 #include <asm/sev.h>
+#include <asm/smp.h>
+#include <asm/spec-ctrl.h>
 
 #ifdef CONFIG_X86_64
 # include <asm/mmconfig.h>
-- 
2.49.0

[PATCH v3 06/44] x86/cpu/topology: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/topology_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index b5a5e1411469..48c47d02d8a9 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -3,8 +3,8 @@
 
 #include <xen/xen.h>
 
-#include <asm/intel-family.h>
 #include <asm/apic.h>
+#include <asm/intel-family.h>
 #include <asm/processor.h>
 #include <asm/smp.h>
 
-- 
2.49.0

[PATCH v3 07/44] x86/mce: Reorder core.c headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/mce/core.c | 62 +++++++++++++++++-----------------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index e9b3c5d4a52e..fe9e65f314fb 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -9,52 +9,52 @@
  * Author: Andi Kleen
  */
 
-#include <linux/thread_info.h>
 #include <linux/capability.h>
-#include <linux/miscdevice.h>
-#include <linux/ratelimit.h>
-#include <linux/rcupdate.h>
-#include <linux/kobject.h>
-#include <linux/uaccess.h>
-#include <linux/kdebug.h>
-#include <linux/kernel.h>
-#include <linux/percpu.h>
-#include <linux/string.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/delay.h>
+#include <linux/cpu.h>
 #include <linux/ctype.h>
-#include <linux/sched.h>
-#include <linux/sysfs.h>
-#include <linux/types.h>
-#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/fs.h>
+#include <linux/hardirq.h>
 #include <linux/init.h>
+#include <linux/irq_work.h>
+#include <linux/kdebug.h>
+#include <linux/kernel.h>
+#include <linux/kexec.h>
 #include <linux/kmod.h>
-#include <linux/poll.h>
+#include <linux/kobject.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
 #include <linux/nmi.h>
-#include <linux/cpu.h>
+#include <linux/percpu.h>
+#include <linux/poll.h>
 #include <linux/ras.h>
-#include <linux/smp.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/debugfs.h>
-#include <linux/irq_work.h>
-#include <linux/export.h>
+#include <linux/ratelimit.h>
+#include <linux/rcupdate.h>
+#include <linux/sched.h>
 #include <linux/set_memory.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/string.h>
 #include <linux/sync_core.h>
+#include <linux/syscore_ops.h>
+#include <linux/sysfs.h>
 #include <linux/task_work.h>
-#include <linux/hardirq.h>
-#include <linux/kexec.h>
+#include <linux/thread_info.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
 
-#include <asm/fred.h>
 #include <asm/cpu_device_id.h>
-#include <asm/processor.h>
-#include <asm/traps.h>
-#include <asm/tlbflush.h>
+#include <asm/fred.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
+#include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/tdx.h>
+#include <asm/tlbflush.h>
+#include <asm/traps.h>
 
 #include "internal.h"
 
-- 
2.49.0

[PATCH v3 08/44] x86/paravirt: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/paravirt.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index ab3e172dcc69..3d745cd25a43 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -6,34 +6,34 @@
     2007 - x86_64 support added by Glauber de Oliveira Costa, Red Hat Inc
 */
 
+#include <linux/bcd.h>
+#include <linux/efi.h>
 #include <linux/errno.h>
-#include <linux/init.h>
 #include <linux/export.h>
-#include <linux/efi.h>
-#include <linux/bcd.h>
 #include <linux/highmem.h>
+#include <linux/init.h>
 #include <linux/kprobes.h>
 #include <linux/pgtable.h>
 #include <linux/static_call.h>
 
+#include <asm/apic.h>
 #include <asm/bug.h>
-#include <asm/paravirt.h>
 #include <asm/debugreg.h>
+#include <asm/delay.h>
 #include <asm/desc.h>
+#include <asm/fixmap.h>
+#include <asm/gsseg.h>
+#include <asm/io_bitmap.h>
+#include <asm/irq.h>
+#include <asm/msr.h>
+#include <asm/paravirt.h>
+#include <asm/pgalloc.h>
 #include <asm/setup.h>
+#include <asm/special_insns.h>
 #include <asm/time.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/delay.h>
-#include <asm/fixmap.h>
-#include <asm/apic.h>
-#include <asm/tlbflush.h>
 #include <asm/timer.h>
-#include <asm/special_insns.h>
 #include <asm/tlb.h>
-#include <asm/io_bitmap.h>
-#include <asm/gsseg.h>
-#include <asm/msr.h>
+#include <asm/tlbflush.h>
 
 /* stub always returning 0. */
 DEFINE_ASM_FUNC(paravirt_ret0, "xor %eax,%eax", .entry.text);
-- 
2.49.0

[PATCH v3 09/44] x86/perf/zhaoxin: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/events/zhaoxin/core.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 4bdfcf091200..d59992364880 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -5,16 +5,16 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include <linux/stddef.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/slab.h>
 #include <linux/export.h>
+#include <linux/init.h>
 #include <linux/nmi.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
 
+#include <asm/apic.h>
 #include <asm/cpufeature.h>
 #include <asm/hardirq.h>
-#include <asm/apic.h>
 #include <asm/msr.h>
 
 #include "../perf_event.h"
@@ -616,4 +616,3 @@ __init int zhaoxin_pmu_init(void)
 
 	return 0;
 }
-
-- 
2.49.0

[PATCH v3 10/44] x86/resctrl: Reorder core.c headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/resctrl/core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 7109cbfcad4f..289e79154922 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -17,13 +17,14 @@
 #define pr_fmt(fmt)	"resctrl: " fmt
 
 #include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/err.h>
 #include <linux/cpuhotplug.h>
+#include <linux/err.h>
+#include <linux/slab.h>
 
 #include <asm/cpu_device_id.h>
 #include <asm/msr.h>
 #include <asm/resctrl.h>
+
 #include "internal.h"
 
 /*
-- 
2.49.0

[PATCH v3 11/44] x86/tdx: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/coco/tdx/tdx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index 7b2833705d47..7bc11836c46a 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -8,16 +8,17 @@
 #include <linux/export.h>
 #include <linux/io.h>
 #include <linux/kexec.h>
+
 #include <asm/coco.h>
-#include <asm/tdx.h>
-#include <asm/vmx.h>
 #include <asm/ia32.h>
 #include <asm/insn.h>
 #include <asm/insn-eval.h>
 #include <asm/paravirt_types.h>
 #include <asm/pgtable.h>
 #include <asm/set_memory.h>
+#include <asm/tdx.h>
 #include <asm/traps.h>
+#include <asm/vmx.h>
 
 /* MMIO direction */
 #define EPT_READ	0
-- 
2.49.0

[PATCH v3 12/44] cpufreq: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 drivers/cpufreq/speedstep-lib.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 0b66df4ed513..f08817331aec 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -9,14 +9,15 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/cpufreq.h>
+#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
 
 #include <asm/msr.h>
 #include <asm/tsc.h>
+
 #include "speedstep-lib.h"
 
 #define PFX "speedstep-lib: "
-- 
2.49.0

[PATCH v3 13/44] hwmon: (fam15h_power) Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 drivers/hwmon/fam15h_power.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index 8ecebea53651..5a5674e85f63 100644
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -6,20 +6,21 @@
  * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
  */
 
+#include <linux/bitops.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
 #include <linux/err.h>
-#include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
+#include <linux/hwmon.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/pci.h>
-#include <linux/bitops.h>
-#include <linux/cpu.h>
-#include <linux/cpumask.h>
-#include <linux/time.h>
 #include <linux/sched.h>
+#include <linux/time.h>
 #include <linux/topology.h>
-#include <asm/processor.h>
+
 #include <asm/msr.h>
+#include <asm/processor.h>
 
 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
 MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
-- 
2.49.0

[PATCH v3 14/44] hwmon: (k8temp) Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 drivers/hwmon/k8temp.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 2b80ac410cd1..8c1efce9a04b 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -7,13 +7,14 @@
  * Inspired from the w83785 and amd756 drivers.
  */
 
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/pci.h>
-#include <linux/hwmon.h>
 #include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/init.h>
+#include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
 #include <asm/processor.h>
 
 #define TEMP_FROM_REG(val)	(((((val) >> 16) & 0xff) - 49) * 1000)
-- 
2.49.0

[PATCH v3 15/44] perf/x86/amd/uncore: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/events/amd/uncore.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e8b6af199c73..c1483ef16c0b 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -5,18 +5,18 @@
  * Author: Jacob Shin <jacob.shin@amd.com>
  */
 
-#include <linux/perf_event.h>
-#include <linux/percpu.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/init.h>
 #include <linux/cpu.h>
-#include <linux/cpumask.h>
 #include <linux/cpufeature.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/perf_event.h>
+#include <linux/slab.h>
 #include <linux/smp.h>
+#include <linux/types.h>
 
-#include <asm/perf_event.h>
 #include <asm/msr.h>
+#include <asm/perf_event.h>
 
 #define NUM_COUNTERS_NB		4
 #define NUM_COUNTERS_L2		4
-- 
2.49.0

[PATCH v3 16/44] thermal: intel: Reorder headers alphabetically

[Ahmed S. Darwish]

The source file uses cpuid_*() macros, but it does not include
<asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
be included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 drivers/thermal/intel/x86_pkg_temp_thermal.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 3fc679b6f11b..c843cb5fc5c3 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -5,19 +5,19 @@
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/err.h>
 #include <linux/init.h>
 #include <linux/intel_tcc.h>
-#include <linux/err.h>
+#include <linux/module.h>
 #include <linux/param.h>
-#include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/slab.h>
 #include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
 #include <linux/thermal.h>
-#include <linux/debugfs.h>
 
 #include <asm/cpu_device_id.h>
 #include <asm/msr.h>
-- 
2.49.0

[PATCH v3 17/44] treewide: Explicitly include <asm/cpuid/api.h>

[Ahmed S. Darwish]

Let all CPUID call sites which include the main CPUID API header
implicitly though <asm/processor.h> include it explicitly instead.

This disentangles the CPUID API header <asm/cpuid/api.h> from
<asm/processor.h>, thus avoiding a circular header dependency.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/compressed/pgtable_64.c        | 1 +
 arch/x86/boot/startup/sme.c                  | 1 +
 arch/x86/coco/tdx/tdx.c                      | 1 +
 arch/x86/events/amd/core.c                   | 2 ++
 arch/x86/events/amd/ibs.c                    | 1 +
 arch/x86/events/amd/lbr.c                    | 2 ++
 arch/x86/events/amd/power.c                  | 3 +++
 arch/x86/events/amd/uncore.c                 | 1 +
 arch/x86/events/intel/core.c                 | 1 +
 arch/x86/events/intel/lbr.c                  | 1 +
 arch/x86/events/zhaoxin/core.c               | 1 +
 arch/x86/include/asm/acrn.h                  | 2 ++
 arch/x86/include/asm/microcode.h             | 1 +
 arch/x86/include/asm/xen/hypervisor.h        | 1 +
 arch/x86/kernel/cpu/amd.c                    | 1 +
 arch/x86/kernel/cpu/centaur.c                | 1 +
 arch/x86/kernel/cpu/hygon.c                  | 1 +
 arch/x86/kernel/cpu/mce/core.c               | 1 +
 arch/x86/kernel/cpu/mce/inject.c             | 1 +
 arch/x86/kernel/cpu/resctrl/core.c           | 1 +
 arch/x86/kernel/cpu/resctrl/monitor.c        | 1 +
 arch/x86/kernel/cpu/scattered.c              | 1 +
 arch/x86/kernel/cpu/sgx/main.c               | 3 +++
 arch/x86/kernel/cpu/topology_amd.c           | 1 +
 arch/x86/kernel/cpu/topology_common.c        | 1 +
 arch/x86/kernel/cpu/topology_ext.c           | 1 +
 arch/x86/kernel/cpu/transmeta.c              | 3 +++
 arch/x86/kernel/cpu/zhaoxin.c                | 1 +
 arch/x86/kernel/cpuid.c                      | 1 +
 arch/x86/kernel/paravirt.c                   | 1 +
 arch/x86/kvm/cpuid.h                         | 3 +++
 arch/x86/kvm/mmu/spte.c                      | 1 +
 drivers/cpufreq/speedstep-lib.c              | 1 +
 drivers/firmware/efi/libstub/x86-5lvl.c      | 1 +
 drivers/hwmon/fam15h_power.c                 | 1 +
 drivers/hwmon/k10temp.c                      | 2 ++
 drivers/hwmon/k8temp.c                       | 1 +
 drivers/thermal/intel/intel_hfi.c            | 1 +
 drivers/thermal/intel/x86_pkg_temp_thermal.c | 1 +
 39 files changed, 51 insertions(+)

diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index bdd26050dff7..d94d98595780 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -2,6 +2,7 @@
 #include "misc.h"
 #include <asm/bootparam.h>
 #include <asm/bootparam_utils.h>
+#include <asm/cpuid/api.h>
 #include <asm/e820/types.h>
 #include <asm/processor.h>
 #include "../string.h"
diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c
index 922b236be02f..6a58ab568390 100644
--- a/arch/x86/boot/startup/sme.c
+++ b/arch/x86/boot/startup/sme.c
@@ -40,6 +40,7 @@
 #include <linux/mm.h>
 
 #include <asm/coco.h>
+#include <asm/cpuid/api.h>
 #include <asm/init.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index 7bc11836c46a..4ed8ec642646 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -10,6 +10,7 @@
 #include <linux/kexec.h>
 
 #include <asm/coco.h>
+#include <asm/cpuid/api.h>
 #include <asm/ia32.h>
 #include <asm/insn.h>
 #include <asm/insn-eval.h>
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index b20661b8621d..d28d45ceb707 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -7,8 +7,10 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/jiffies.h>
+
 #include <asm/apicdef.h>
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/nmi.h>
 
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 112f43b23ebf..0c7848e6149e 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -15,6 +15,7 @@
 #include <linux/sched/clock.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "../perf_event.h"
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
index d24da377df77..5b437dc8e4ce 100644
--- a/arch/x86/events/amd/lbr.c
+++ b/arch/x86/events/amd/lbr.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/perf_event.h>
+
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/perf_event.h>
 
diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c
index dad42790cf7d..744dffa42dee 100644
--- a/arch/x86/events/amd/power.c
+++ b/arch/x86/events/amd/power.c
@@ -10,8 +10,11 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/perf_event.h>
+
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
+
 #include "../perf_event.h"
 
 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index c1483ef16c0b..5261f12007df 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -15,6 +15,7 @@
 #include <linux/smp.h>
 #include <linux/types.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/perf_event.h>
 
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 741b229f0718..a372f0e2867a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -17,6 +17,7 @@
 #include <linux/kvm_host.h>
 
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/hardirq.h>
 #include <asm/intel-family.h>
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 7aa59966e7c3..0d1ec3651735 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -3,6 +3,7 @@
 #include <linux/types.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index d59992364880..15bb9c9c9358 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -14,6 +14,7 @@
 
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/hardirq.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h
index fab11192c60a..db42b477c41d 100644
--- a/arch/x86/include/asm/acrn.h
+++ b/arch/x86/include/asm/acrn.h
@@ -2,6 +2,8 @@
 #ifndef _ASM_X86_ACRN_H
 #define _ASM_X86_ACRN_H
 
+#include <asm/cpuid/api.h>
+
 /*
  * This CPUID returns feature bitmaps in EAX.
  * Guest VM uses this to detect the appropriate feature bit.
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 8b41f26f003b..645e65ac1586 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -3,6 +3,7 @@
 #define _ASM_X86_MICROCODE_H
 
 #include <asm/msr.h>
+#include <asm/cpuid/api.h>
 
 struct cpu_signature {
 	unsigned int sig;
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index c2fc7869b996..7c596cebfb78 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -37,6 +37,7 @@ extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
 
 #include <asm/bug.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 #define XEN_SIGNATURE "XenVMMXenVMM"
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index c988d876b700..f982b3bb1c10 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -14,6 +14,7 @@
 #include <asm/cacheinfo.h>
 #include <asm/cpu.h>
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/delay.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index a3b55db35c96..cc5a390dcd07 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -5,6 +5,7 @@
 
 #include <asm/cpu.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/e820/api.h>
 #include <asm/mtrr.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 2154f12766fb..75ad7eb1301a 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -10,6 +10,7 @@
 
 #include <asm/apic.h>
 #include <asm/cpu.h>
+#include <asm/cpuid/api.h>
 #include <asm/smp.h>
 #include <asm/numa.h>
 #include <asm/cacheinfo.h>
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index fe9e65f314fb..9f7c39b4163f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -47,6 +47,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/fred.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index d02c4f556cd0..42c82c14c48a 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -26,6 +26,7 @@
 
 #include <asm/amd/nb.h>
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/irq_vectors.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 289e79154922..9498d55d51e6 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/resctrl.h>
 
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index c261558276cd..5dffb9453d77 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -21,6 +21,7 @@
 #include <linux/resctrl.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "internal.h"
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 3d23b943f596..15f8752d4132 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -5,6 +5,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/processor.h>
 
diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c
index 2de01b379aa3..00bf42f4c536 100644
--- a/arch/x86/kernel/cpu/sgx/main.c
+++ b/arch/x86/kernel/cpu/sgx/main.c
@@ -14,8 +14,11 @@
 #include <linux/slab.h>
 #include <linux/sysfs.h>
 #include <linux/vmalloc.h>
+
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/sgx.h>
+
 #include "driver.h"
 #include "encl.h"
 #include "encls.h"
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index 843b1655ab45..abc6f5a7a486 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -2,6 +2,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index 48c47d02d8a9..38189e4fea0e 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -4,6 +4,7 @@
 #include <xen/xen.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/intel-family.h>
 #include <asm/processor.h>
 #include <asm/smp.h>
diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topology_ext.c
index 467b0326bf1a..eb915c73895f 100644
--- a/arch/x86/kernel/cpu/topology_ext.c
+++ b/arch/x86/kernel/cpu/topology_ext.c
@@ -2,6 +2,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/processor.h>
 
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 42c939827621..1fdcd69c625c 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -3,8 +3,11 @@
 #include <linux/sched.h>
 #include <linux/sched/clock.h>
 #include <linux/mm.h>
+
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
+
 #include "cpu.h"
 
 static void early_init_transmeta(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 89b1c8a70fe8..cfcfb6221e3f 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -4,6 +4,7 @@
 
 #include <asm/cpu.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "cpu.h"
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index dae436253de4..cbd04b677fd1 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -37,6 +37,7 @@
 #include <linux/gfp.h>
 #include <linux/completion.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 3d745cd25a43..b7fc3b78086c 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -18,6 +18,7 @@
 
 #include <asm/apic.h>
 #include <asm/bug.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/delay.h>
 #include <asm/desc.h>
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index d3f5ae15a7ca..89f8ed3fb37a 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -3,8 +3,11 @@
 #define ARCH_X86_KVM_CPUID_H
 
 #include "reverse_cpuid.h"
+
 #include <asm/cpu.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
+
 #include <uapi/asm/kvm_para.h>
 
 extern u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
index cfce03d8f123..e7b69275ae50 100644
--- a/arch/x86/kvm/mmu/spte.c
+++ b/arch/x86/kvm/mmu/spte.c
@@ -15,6 +15,7 @@
 #include "x86.h"
 #include "spte.h"
 
+#include <asm/cpuid/api.h>
 #include <asm/e820/api.h>
 #include <asm/memtype.h>
 #include <asm/vmx.h>
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index f08817331aec..3c323cd8eede 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/tsc.h>
 
diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
index f1c5fb45d5f7..029ad80cf0b4 100644
--- a/drivers/firmware/efi/libstub/x86-5lvl.c
+++ b/drivers/firmware/efi/libstub/x86-5lvl.c
@@ -2,6 +2,7 @@
 #include <linux/efi.h>
 
 #include <asm/boot.h>
+#include <asm/cpuid/api.h>
 #include <asm/desc.h>
 #include <asm/efi.h>
 
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index 5a5674e85f63..1ecaef25f04e 100644
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -19,6 +19,7 @@
 #include <linux/time.h>
 #include <linux/topology.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index babf2413d666..12115654689a 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -20,7 +20,9 @@
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/pci_ids.h>
+
 #include <asm/amd/node.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 8c1efce9a04b..eb167be245b9 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -15,6 +15,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 #define TEMP_FROM_REG(val)	(((((val) >> 16) & 0xff) - 49) * 1000)
diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c
index bd2fca7dc017..c910cc563d9d 100644
--- a/drivers/thermal/intel/intel_hfi.c
+++ b/drivers/thermal/intel/intel_hfi.c
@@ -41,6 +41,7 @@
 #include <linux/topology.h>
 #include <linux/workqueue.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "intel_hfi.h"
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index c843cb5fc5c3..1b9e0b49856c 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -20,6 +20,7 @@
 #include <linux/thermal.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "thermal_interrupt.h"
-- 
2.49.0

[PATCH v3 18/44] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs

[Ahmed S. Darwish]

A new CPUID model will be added where its APIs will be designated as the
"official" CPUID API.  Free the cpuid_leaf() and cpuid_subleaf() function
names for that model.  Rename them accordingly to cpuid_read() and
cpuid_read_subleaf().

Note, for kernel/cpuid.c, rename its local file operations read function
from cpuid_read() to cpuid_read_f() so that it does not conflict with the
new names.

No functional change.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h   | 6 +++---
 arch/x86/kernel/cpu/topology_amd.c | 2 +-
 arch/x86/kernel/cpu/topology_ext.c | 2 +-
 arch/x86/kernel/cpuid.c            | 5 ++---
 4 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 44fa82e1267c..2b9750cc8a75 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -131,12 +131,12 @@ static inline void __cpuid_read(u32 leaf, u32 subleaf, u32 *regs)
 	__cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUID_EDX);
 }
 
-#define cpuid_subleaf(leaf, subleaf, regs) {		\
+#define cpuid_read_subleaf(leaf, subleaf, regs) {	\
 	static_assert(sizeof(*(regs)) == 16);		\
 	__cpuid_read(leaf, subleaf, (u32 *)(regs));	\
 }
 
-#define cpuid_leaf(leaf, regs) {			\
+#define cpuid_read(leaf, regs) {			\
 	static_assert(sizeof(*(regs)) == 16);		\
 	__cpuid_read(leaf, 0, (u32 *)(regs));		\
 }
@@ -228,7 +228,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves)
  */
 static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
 {
-	cpuid_leaf(0x2, regs);
+	cpuid_read(0x2, regs);
 
 	/*
 	 * All Intel CPUs must report an iteration count of 1.	In case
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index abc6f5a7a486..c6bedae12a7e 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -80,7 +80,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool has_topoext)
 	if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
 		return false;
 
-	cpuid_leaf(0x8000001e, &leaf);
+	cpuid_read(0x8000001e, &leaf);
 
 	tscan->c->topo.initial_apicid = leaf.ext_apic_id;
 
diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topology_ext.c
index eb915c73895f..60dfaa02ffd0 100644
--- a/arch/x86/kernel/cpu/topology_ext.c
+++ b/arch/x86/kernel/cpu/topology_ext.c
@@ -71,7 +71,7 @@ static inline bool topo_subleaf(struct topo_scan *tscan, u32 leaf, u32 subleaf,
 	default: return false;
 	}
 
-	cpuid_subleaf(leaf, subleaf, &sl);
+	cpuid_read_subleaf(leaf, subleaf, &sl);
 
 	if (!sl.num_processors || sl.type == INVALID_TYPE)
 		return false;
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index cbd04b677fd1..b55fe9c7359a 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -59,8 +59,7 @@ static void cpuid_smp_cpuid(void *cmd_block)
 	complete(&cmd->done);
 }
 
-static ssize_t cpuid_read(struct file *file, char __user *buf,
-			  size_t count, loff_t *ppos)
+static ssize_t cpuid_read_f(struct file *file, char __user *buf, size_t count, loff_t *ppos)
 {
 	char __user *tmp = buf;
 	struct cpuid_regs_done cmd;
@@ -120,7 +119,7 @@ static int cpuid_open(struct inode *inode, struct file *file)
 static const struct file_operations cpuid_fops = {
 	.owner = THIS_MODULE,
 	.llseek = no_seek_end_llseek,
-	.read = cpuid_read,
+	.read = cpuid_read_f,
 	.open = cpuid_open,
 };
 
-- 
2.49.0

[PATCH v3 19/44] x86/cpuid: Introduce <asm/cpuid/leaf_types.h>

[Ahmed S. Darwish]

To centralize CPUID access across the x86 subsystem, introduce
<asm/cpuid/leaf_types.h>.  It is generated by the x86-cpuid-db project
and includes detailed C99 bitfield listings for all publicly known CPUID
leaves.

Add the header to MAINTAINERS x86 CPUID database entry.

Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.4/CHANGELOG.rst
---
 MAINTAINERS                             |    1 +
 arch/x86/include/asm/cpuid/leaf_types.h | 2055 +++++++++++++++++++++++
 2 files changed, 2056 insertions(+)
 create mode 100644 arch/x86/include/asm/cpuid/leaf_types.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a92290fffa16..b8ac0a663e55 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26819,6 +26819,7 @@ R:	Ahmed S. Darwish <darwi@linutronix.de>
 L:	x86-cpuid@lists.linux.dev
 S:	Maintained
 W:	https://x86-cpuid.org
+F:	arch/x86/include/asm/cpuid/leaf_types.h
 F:	tools/arch/x86/kcpuid/
 
 X86 ENTRY CODE
diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm/cpuid/leaf_types.h
new file mode 100644
index 000000000000..0af2f67aee40
--- /dev/null
+++ b/arch/x86/include/asm/cpuid/leaf_types.h
@@ -0,0 +1,2055 @@
+/* SPDX-License-Identifier: MIT */
+/* Generator: x86-cpuid-db v2.4 */
+
+/*
+ * Auto-generated file.
+ * Please submit all updates and bugfixes to https://x86-cpuid.org
+ */
+
+#ifndef _ASM_X86_CPUID_LEAVES
+#define _ASM_X86_CPUID_LEAVES
+
+#include <linux/types.h>
+
+/*
+ * Leaf 0x0
+ * Maximum standard leaf number + CPU vendor string
+ */
+
+struct leaf_0x0_0 {
+	// eax
+	u32	max_std_leaf			: 32; // Highest standard CPUID leaf supported
+	// ebx
+	u32	cpu_vendorid_0			: 32; // CPU vendor ID string bytes 0 - 3
+	// ecx
+	u32	cpu_vendorid_2			: 32; // CPU vendor ID string bytes 8 - 11
+	// edx
+	u32	cpu_vendorid_1			: 32; // CPU vendor ID string bytes 4 - 7
+};
+
+/*
+ * Leaf 0x1
+ * CPU FMS (Family/Model/Stepping) + standard feature flags
+ */
+
+struct leaf_0x1_0 {
+	// eax
+	u32	stepping			:  4, // Stepping ID
+		base_model			:  4, // Base CPU model ID
+		base_family_id			:  4, // Base CPU family ID
+		cpu_type			:  2, // CPU type
+						:  2, // Reserved
+		ext_model			:  4, // Extended CPU model ID
+		ext_family			:  8, // Extended CPU family ID
+						:  4; // Reserved
+	// ebx
+	u32	brand_id			:  8, // Brand index
+		clflush_size			:  8, // CLFLUSH instruction cache line size
+		n_logical_cpu			:  8, // Logical CPU count
+		local_apic_id			:  8; // Initial local APIC physical ID
+	// ecx
+	u32	sse3				:  1, // Streaming SIMD Extensions 3 (SSE3)
+		pclmulqdq			:  1, // PCLMULQDQ instruction support
+		dtes64				:  1, // 64-bit DS save area
+		monitor				:  1, // MONITOR/MWAIT support
+		dscpl				:  1, // CPL Qualified Debug Store
+		vmx				:  1, // Virtual Machine Extensions
+		smx				:  1, // Safer Mode Extensions
+		est				:  1, // Enhanced Intel SpeedStep
+		tm2				:  1, // Thermal Monitor 2
+		ssse3				:  1, // Supplemental SSE3
+		cntxt_id			:  1, // L1 Context ID
+		sdbg				:  1, // Silicon Debug
+		fma				:  1, // FMA extensions using YMM state
+		cx16				:  1, // CMPXCHG16B instruction support
+		xtpr_update			:  1, // xTPR Update Control
+		pdcm				:  1, // Perfmon and Debug Capability
+						:  1, // Reserved
+		pcid				:  1, // Process-context identifiers
+		dca				:  1, // Direct Cache Access
+		sse4_1				:  1, // SSE4.1
+		sse4_2				:  1, // SSE4.2
+		x2apic				:  1, // X2APIC support
+		movbe				:  1, // MOVBE instruction support
+		popcnt				:  1, // POPCNT instruction support
+		tsc_deadline_timer		:  1, // APIC timer one-shot operation
+		aes				:  1, // AES instructions
+		xsave				:  1, // XSAVE (and related instructions) support
+		osxsave				:  1, // XSAVE (and related instructions) are enabled by OS
+		avx				:  1, // AVX instructions support
+		f16c				:  1, // Half-precision floating-point conversion support
+		rdrand				:  1, // RDRAND instruction support
+		guest_status			:  1; // System is running as guest; (para-)virtualized system
+	// edx
+	u32	fpu				:  1, // Floating-Point Unit on-chip (x87)
+		vme				:  1, // Virtual-8086 Mode Extensions
+		de				:  1, // Debugging Extensions
+		pse				:  1, // Page Size Extension
+		tsc				:  1, // Time Stamp Counter
+		msr				:  1, // Model-Specific Registers (RDMSR and WRMSR support)
+		pae				:  1, // Physical Address Extensions
+		mce				:  1, // Machine Check Exception
+		cx8				:  1, // CMPXCHG8B instruction
+		apic				:  1, // APIC on-chip
+						:  1, // Reserved
+		sep				:  1, // SYSENTER, SYSEXIT, and associated MSRs
+		mtrr				:  1, // Memory Type Range Registers
+		pge				:  1, // Page Global Extensions
+		mca				:  1, // Machine Check Architecture
+		cmov				:  1, // Conditional Move Instruction
+		pat				:  1, // Page Attribute Table
+		pse36				:  1, // Page Size Extension (36-bit)
+		psn				:  1, // Processor Serial Number
+		clflush				:  1, // CLFLUSH instruction
+						:  1, // Reserved
+		ds				:  1, // Debug Store
+		acpi				:  1, // Thermal monitor and clock control
+		mmx				:  1, // MMX instructions
+		fxsr				:  1, // FXSAVE and FXRSTOR instructions
+		sse				:  1, // SSE instructions
+		sse2				:  1, // SSE2 instructions
+		selfsnoop			:  1, // Self Snoop
+		htt				:  1, // Hyper-threading
+		tm				:  1, // Thermal Monitor
+		ia64				:  1, // Legacy IA-64 (Itanium) support bit, now reserved
+		pbe				:  1; // Pending Break Enable
+};
+
+/*
+ * Leaf 0x2
+ * Intel cache and TLB information one-byte descriptors
+ */
+
+struct leaf_0x2_0 {
+	// eax
+	u32	iteration_count			:  8, // Number of times this leaf must be queried
+		desc1				:  8, // Descriptor #1
+		desc2				:  8, // Descriptor #2
+		desc3				:  7, // Descriptor #3
+		eax_invalid			:  1; // Descriptors 1-3 are invalid if set
+	// ebx
+	u32	desc4				:  8, // Descriptor #4
+		desc5				:  8, // Descriptor #5
+		desc6				:  8, // Descriptor #6
+		desc7				:  7, // Descriptor #7
+		ebx_invalid			:  1; // Descriptors 4-7 are invalid if set
+	// ecx
+	u32	desc8				:  8, // Descriptor #8
+		desc9				:  8, // Descriptor #9
+		desc10				:  8, // Descriptor #10
+		desc11				:  7, // Descriptor #11
+		ecx_invalid			:  1; // Descriptors 8-11 are invalid if set
+	// edx
+	u32	desc12				:  8, // Descriptor #12
+		desc13				:  8, // Descriptor #13
+		desc14				:  8, // Descriptor #14
+		desc15				:  7, // Descriptor #15
+		edx_invalid			:  1; // Descriptors 12-15 are invalid if set
+};
+
+/*
+ * Leaf 0x4
+ * Intel deterministic cache parameters
+ */
+
+struct leaf_0x4_0 {
+	// eax
+	u32	cache_type			:  5, // Cache type field
+		cache_level			:  3, // Cache level (1-based)
+		cache_self_init			:  1, // Self-initializing cache level
+		fully_associative		:  1, // Fully-associative cache
+						:  4, // Reserved
+		num_threads_sharing		: 12, // Number logical CPUs sharing this cache
+		num_cores_on_die		:  6; // Number of cores in the physical package
+	// ebx
+	u32	cache_linesize			: 12, // System coherency line size (0-based)
+		cache_npartitions		: 10, // Physical line partitions (0-based)
+		cache_nways			: 10; // Ways of associativity (0-based)
+	// ecx
+	u32	cache_nsets			: 31, // Cache number of sets (0-based)
+						:  1; // Reserved
+	// edx
+	u32	wbinvd_rll_no_guarantee		:  1, // WBINVD/INVD not guaranteed for Remote Lower-Level caches
+		ll_inclusive			:  1, // Cache is inclusive of Lower-Level caches
+		complex_indexing		:  1, // Not a direct-mapped cache (complex function)
+						: 29; // Reserved
+};
+
+/*
+ * Leaf 0x5
+ * MONITOR/MWAIT instructions enumeration
+ */
+
+struct leaf_0x5_0 {
+	// eax
+	u32	min_mon_size			: 16, // Smallest monitor-line size, in bytes
+						: 16; // Reserved
+	// ebx
+	u32	max_mon_size			: 16, // Largest monitor-line size, in bytes
+						: 16; // Reserved
+	// ecx
+	u32	mwait_ext			:  1, // Enumeration of MONITOR/MWAIT extensions is supported
+		mwait_irq_break			:  1, // Interrupts as a break-event for MWAIT is supported
+						: 30; // Reserved
+	// edx
+	u32	n_c0_substates			:  4, // Number of C0 sub C-states supported using MWAIT
+		n_c1_substates			:  4, // Number of C1 sub C-states supported using MWAIT
+		n_c2_substates			:  4, // Number of C2 sub C-states supported using MWAIT
+		n_c3_substates			:  4, // Number of C3 sub C-states supported using MWAIT
+		n_c4_substates			:  4, // Number of C4 sub C-states supported using MWAIT
+		n_c5_substates			:  4, // Number of C5 sub C-states supported using MWAIT
+		n_c6_substates			:  4, // Number of C6 sub C-states supported using MWAIT
+		n_c7_substates			:  4; // Number of C7 sub C-states supported using MWAIT
+};
+
+/*
+ * Leaf 0x6
+ * Thermal and Power Management enumeration
+ */
+
+struct leaf_0x6_0 {
+	// eax
+	u32	digital_temp			:  1, // Digital temperature sensor
+		turbo_boost			:  1, // Intel Turbo Boost
+		lapic_timer_always_on		:  1, // Always-Running APIC Timer (not affected by p-state)
+						:  1, // Reserved
+		power_limit_event		:  1, // Power Limit Notification (PLN) event
+		ecmd				:  1, // Clock modulation duty cycle extension
+		package_thermal			:  1, // Package thermal management
+		hwp_base_regs			:  1, // HWP (Hardware P-states) base registers are supported
+		hwp_notify			:  1, // HWP notification (IA32_HWP_INTERRUPT MSR)
+		hwp_activity_window		:  1, // HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
+		hwp_energy_perf_pr		:  1, // HWP Energy Performance Preference
+		hwp_package_req			:  1, // HWP Package Level Request
+						:  1, // Reserved
+		hdc_base_regs			:  1, // HDC base registers are supported
+		turbo_boost_3_0			:  1, // Intel Turbo Boost Max 3.0
+		hwp_capabilities		:  1, // HWP Highest Performance change
+		hwp_peci_override		:  1, // HWP PECI override
+		hwp_flexible			:  1, // Flexible HWP
+		hwp_fast			:  1, // IA32_HWP_REQUEST MSR fast access mode
+		hw_feedback			:  1, // HW_FEEDBACK MSRs supported
+		hwp_ignore_idle			:  1, // Ignoring idle logical CPU HWP req is supported
+						:  2, // Reserved
+		thread_director			:  1, // Intel thread director support
+		therm_interrupt_bit25		:  1, // IA32_THERM_INTERRUPT MSR bit 25 is supported
+						:  7; // Reserved
+	// ebx
+	u32	n_therm_thresholds		:  4, // Digital thermometer thresholds
+						: 28; // Reserved
+	// ecx
+	u32	aperf_mperf			:  1, // MPERF/APERF MSRs (effective frequency interface)
+						:  2, // Reserved
+		energy_perf_bias		:  1, // IA32_ENERGY_PERF_BIAS MSR support
+						:  4, // Reserved
+		thrd_director_nclasses		:  8, // Number of classes, Intel thread director
+						: 16; // Reserved
+	// edx
+	u32	perfcap_reporting		:  1, // Performance capability reporting
+		encap_reporting			:  1, // Energy efficiency capability reporting
+						:  6, // Reserved
+		feedback_sz			:  4, // Feedback interface structure size, in 4K pages
+						:  4, // Reserved
+		this_lcpu_hwfdbk_idx		: 16; // This logical CPU hardware feedback interface index
+};
+
+/*
+ * Leaf 0x7
+ * Extended CPU features enumeration
+ */
+
+struct leaf_0x7_0 {
+	// eax
+	u32	leaf7_n_subleaves		: 32; // Number of leaf 0x7 subleaves
+	// ebx
+	u32	fsgsbase			:  1, // FSBASE/GSBASE read/write support
+		tsc_adjust			:  1, // IA32_TSC_ADJUST MSR supported
+		sgx				:  1, // Intel SGX (Software Guard Extensions)
+		bmi1				:  1, // Bit manipulation extensions group 1
+		hle				:  1, // Hardware Lock Elision
+		avx2				:  1, // AVX2 instruction set
+		fdp_excptn_only			:  1, // FPU Data Pointer updated only on x87 exceptions
+		smep				:  1, // Supervisor Mode Execution Protection
+		bmi2				:  1, // Bit manipulation extensions group 2
+		erms				:  1, // Enhanced REP MOVSB/STOSB
+		invpcid				:  1, // INVPCID instruction (Invalidate Processor Context ID)
+		rtm				:  1, // Intel restricted transactional memory
+		pqm				:  1, // Intel RDT-CMT / AMD Platform-QoS cache monitoring
+		zero_fcs_fds			:  1, // Deprecated FPU CS/DS (stored as zero)
+		mpx				:  1, // Intel memory protection extensions
+		rdt_a				:  1, // Intel RDT / AMD Platform-QoS Enforcement
+		avx512f				:  1, // AVX-512 foundation instructions
+		avx512dq			:  1, // AVX-512 double/quadword instructions
+		rdseed				:  1, // RDSEED instruction
+		adx				:  1, // ADCX/ADOX instructions
+		smap				:  1, // Supervisor mode access prevention
+		avx512ifma			:  1, // AVX-512 integer fused multiply add
+						:  1, // Reserved
+		clflushopt			:  1, // CLFLUSHOPT instruction
+		clwb				:  1, // CLWB instruction
+		intel_pt			:  1, // Intel processor trace
+		avx512pf			:  1, // AVX-512 prefetch instructions
+		avx512er			:  1, // AVX-512 exponent/reciprocal instructions
+		avx512cd			:  1, // AVX-512 conflict detection instructions
+		sha				:  1, // SHA/SHA256 instructions
+		avx512bw			:  1, // AVX-512 byte/word instructions
+		avx512vl			:  1; // AVX-512 VL (128/256 vector length) extensions
+	// ecx
+	u32	prefetchwt1			:  1, // PREFETCHWT1 (Intel Xeon Phi only)
+		avx512vbmi			:  1, // AVX-512 Vector byte manipulation instructions
+		umip				:  1, // User mode instruction protection
+		pku				:  1, // Protection keys for user-space
+		ospke				:  1, // OS protection keys enable
+		waitpkg				:  1, // WAITPKG instructions
+		avx512_vbmi2			:  1, // AVX-512 vector byte manipulation instructions group 2
+		cet_ss				:  1, // CET shadow stack features
+		gfni				:  1, // Galois field new instructions
+		vaes				:  1, // Vector AES instructions
+		vpclmulqdq			:  1, // VPCLMULQDQ 256-bit instruction support
+		avx512_vnni			:  1, // Vector neural network instructions
+		avx512_bitalg			:  1, // AVX-512 bitwise algorithms
+		tme				:  1, // Intel total memory encryption
+		avx512_vpopcntdq		:  1, // AVX-512: POPCNT for vectors of DWORD/QWORD
+						:  1, // Reserved
+		la57				:  1, // 57-bit linear addresses (five-level paging)
+		mawau_val_lm			:  5, // BNDLDX/BNDSTX MAWAU value in 64-bit mode
+		rdpid				:  1, // RDPID instruction
+		key_locker			:  1, // Intel key locker support
+		bus_lock_detect			:  1, // OS bus-lock detection
+		cldemote			:  1, // CLDEMOTE instruction
+						:  1, // Reserved
+		movdiri				:  1, // MOVDIRI instruction
+		movdir64b			:  1, // MOVDIR64B instruction
+		enqcmd				:  1, // Enqueue stores supported (ENQCMD{,S})
+		sgx_lc				:  1, // Intel SGX launch configuration
+		pks				:  1; // Protection keys for supervisor-mode pages
+	// edx
+	u32					:  1, // Reserved
+		sgx_keys			:  1, // Intel SGX attestation services
+		avx512_4vnniw			:  1, // AVX-512 neural network instructions
+		avx512_4fmaps			:  1, // AVX-512 multiply accumulation single precision
+		fsrm				:  1, // Fast short REP MOV
+		uintr				:  1, // CPU supports user interrupts
+						:  2, // Reserved
+		avx512_vp2intersect		:  1, // VP2INTERSECT{D,Q} instructions
+		srdbs_ctrl			:  1, // SRBDS mitigation MSR available
+		md_clear			:  1, // VERW MD_CLEAR microcode support
+		rtm_always_abort		:  1, // XBEGIN (RTM transaction) always aborts
+						:  1, // Reserved
+		tsx_force_abort			:  1, // MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported
+		serialize			:  1, // SERIALIZE instruction
+		hybrid_cpu			:  1, // The CPU is identified as a 'hybrid part'
+		tsxldtrk			:  1, // TSX suspend/resume load address tracking
+						:  1, // Reserved
+		pconfig				:  1, // PCONFIG instruction
+		arch_lbr			:  1, // Intel architectural LBRs
+		cet_ibt				:  1, // CET indirect branch tracking
+						:  1, // Reserved
+		amx_bf16			:  1, // AMX-BF16: tile bfloat16 support
+		avx512_fp16			:  1, // AVX-512 FP16 instructions
+		amx_tile			:  1, // AMX-TILE: tile architecture support
+		amx_int8			:  1, // AMX-INT8: tile 8-bit integer support
+		spec_ctrl			:  1, // Speculation Control (IBRS/IBPB: indirect branch restrictions)
+		intel_stibp			:  1, // Single thread indirect branch predictors
+		flush_l1d			:  1, // FLUSH L1D cache: IA32_FLUSH_CMD MSR
+		arch_capabilities		:  1, // Intel IA32_ARCH_CAPABILITIES MSR
+		core_capabilities		:  1, // IA32_CORE_CAPABILITIES MSR
+		spec_ctrl_ssbd			:  1; // Speculative store bypass disable
+};
+
+struct leaf_0x7_1 {
+	// eax
+	u32					:  4, // Reserved
+		avx_vnni			:  1, // AVX-VNNI instructions
+		avx512_bf16			:  1, // AVX-512 bfloat16 instructions
+		lass				:  1, // Linear address space separation
+		cmpccxadd			:  1, // CMPccXADD instructions
+		arch_perfmon_ext		:  1, // ArchPerfmonExt: leaf 0x23 is supported
+						:  1, // Reserved
+		fzrm				:  1, // Fast zero-length REP MOVSB
+		fsrs				:  1, // Fast short REP STOSB
+		fsrc				:  1, // Fast Short REP CMPSB/SCASB
+						:  4, // Reserved
+		fred				:  1, // FRED: Flexible return and event delivery transitions
+		lkgs				:  1, // LKGS: Load 'kernel' (userspace) GS
+		wrmsrns				:  1, // WRMSRNS instruction (WRMSR-non-serializing)
+		nmi_src				:  1, // NMI-source reporting with FRED event data
+		amx_fp16			:  1, // AMX-FP16: FP16 tile operations
+		hreset 				:  1, // History reset support
+		avx_ifma			:  1, // Integer fused multiply add
+						:  2, // Reserved
+		lam				:  1, // Linear address masking
+		rd_wr_msrlist			:  1, // RDMSRLIST/WRMSRLIST instructions
+						:  4; // Reserved
+	// ebx
+	u32	intel_ppin			:  1, // Protected processor inventory number (PPIN{,_CTL} MSRs)
+						: 31; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					:  4, // Reserved
+		avx_vnni_int8			:  1, // AVX-VNNI-INT8 instructions
+		avx_ne_convert			:  1, // AVX-NE-CONVERT instructions
+						:  2, // Reserved
+		amx_complex			:  1, // AMX-COMPLEX instructions (starting from Granite Rapids)
+						:  5, // Reserved
+		prefetchit_0_1			:  1, // PREFETCHIT0/1 instructions
+						:  3, // Reserved
+		cet_sss				:  1, // CET supervisor shadow stacks safe to use
+						: 13; // Reserved
+};
+
+struct leaf_0x7_2 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	intel_psfd			:  1, // Intel predictive store forward disable
+		ipred_ctrl			:  1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
+		rrsba_ctrl			:  1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
+		ddp_ctrl			:  1, // MSR bit  IA32_SPEC_CTRL.DDPD_U
+		bhi_ctrl			:  1, // MSR bit  IA32_SPEC_CTRL.BHI_DIS_S
+		mcdt_no				:  1, // MCDT mitigation not needed
+		uclock_disable			:  1, // UC-lock disable is supported
+						: 25; // Reserved
+};
+
+/*
+ * Leaf 0x9
+ * Intel DCA (Direct Cache Access) enumeration
+ */
+
+struct leaf_0x9_0 {
+	// eax
+	u32	dca_enabled_in_bios		:  1, // DCA is enabled in BIOS
+						: 31; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0xa
+ * Intel PMU (Performance Monitoring Unit) enumeration
+ */
+
+struct leaf_0xa_0 {
+	// eax
+	u32	pmu_version			:  8, // Performance monitoring unit version ID
+		pmu_n_gcounters			:  8, // Number of general PMU counters per logical CPU
+		pmu_gcounters_nbits		:  8, // Bitwidth of PMU general counters
+		pmu_cpuid_ebx_bits		:  8; // Length of leaf 0xa EBX bit vector
+	// ebx
+	u32	no_core_cycle_evt		:  1, // Core cycle event not available
+		no_insn_retired_evt		:  1, // Instruction retired event not available
+		no_refcycle_evt			:  1, // Reference cycles event not available
+		no_llc_ref_evt			:  1, // LLC-reference event not available
+		no_llc_miss_evt			:  1, // LLC-misses event not available
+		no_br_insn_ret_evt		:  1, // Branch instruction retired event not available
+		no_br_mispredict_evt		:  1, // Branch mispredict retired event not available
+		no_td_slots_evt			:  1, // Topdown slots event not available
+						: 24; // Reserved
+	// ecx
+	u32	pmu_fcounters_bitmap		: 32; // Fixed-function PMU counters support bitmap
+	// edx
+	u32	pmu_n_fcounters			:  5, // Number of fixed PMU counters
+		pmu_fcounters_nbits		:  8, // Bitwidth of PMU fixed counters
+						:  2, // Reserved
+		anythread_depr			:  1, // AnyThread deprecation
+						: 16; // Reserved
+};
+
+/*
+ * Leaf 0xb
+ * CPUs v1 extended topology enumeration
+ */
+
+struct leaf_0xb_0 {
+	// eax
+	u32	x2apic_id_shift			:  5, // Bit width of this level (previous levels inclusive)
+						: 27; // Reserved
+	// ebx
+	u32	domain_lcpus_count		: 16, // Logical CPUs count across all instances of this domain
+						: 16; // Reserved
+	// ecx
+	u32	domain_nr			:  8, // This domain level (subleaf ID)
+		domain_type			:  8, // This domain type
+						: 16; // Reserved
+	// edx
+	u32	x2apic_id			: 32; // x2APIC ID of current logical CPU
+};
+
+/*
+ * Leaf 0xd
+ * Processor extended state enumeration
+ */
+
+struct leaf_0xd_0 {
+	// eax
+	u32	xcr0_x87			:  1, // XCR0.X87 (bit 0) supported
+		xcr0_sse			:  1, // XCR0.SEE (bit 1) supported
+		xcr0_avx			:  1, // XCR0.AVX (bit 2) supported
+		xcr0_mpx_bndregs		:  1, // XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
+		xcr0_mpx_bndcsr			:  1, // XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)
+		xcr0_avx512_opmask		:  1, // XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
+		xcr0_avx512_zmm_hi256		:  1, // XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
+		xcr0_avx512_hi16_zmm		:  1, // XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
+						:  1, // Reserved
+		xcr0_pkru			:  1, // XCR0.PKRU (bit 9) supported (XSAVE PKRU registers)
+						:  1, // Reserved
+		xcr0_cet_u			:  1, // XCR0.CET_U (bit 11) supported (CET user state)
+		xcr0_cet_s			:  1, // XCR0.CET_S (bit 12) supported (CET supervisor state)
+						:  4, // Reserved
+		xcr0_tileconfig			:  1, // XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
+		xcr0_tiledata			:  1, // XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
+						: 13; // Reserved
+	// ebx
+	u32	xsave_sz_xcr0_enabled		: 32; // XSAVE/XRSTOR area byte size, for XCR0 enabled features
+	// ecx
+	u32	xsave_sz_max			: 32; // XSAVE/XRSTOR area max byte size, all CPU features
+	// edx
+	u32					: 30, // Reserved
+		xcr0_lwp			:  1, // AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
+						:  1; // Reserved
+};
+
+struct leaf_0xd_1 {
+	// eax
+	u32	xsaveopt			:  1, // XSAVEOPT instruction
+		xsavec				:  1, // XSAVEC instruction
+		xgetbv1				:  1, // XGETBV instruction with ECX = 1
+		xsaves				:  1, // XSAVES/XRSTORS instructions (and XSS MSR)
+		xfd				:  1, // Extended feature disable support
+						: 27; // Reserved
+	// ebx
+	u32	xsave_sz_xcr0_xmms_enabled	: 32; // XSAVE area size, all XCR0 and XMMS features enabled
+	// ecx
+	u32					:  8, // Reserved
+		xss_pt				:  1, // PT state, supported
+						:  1, // Reserved
+		xss_pasid			:  1, // PASID state, supported
+		xss_cet_u			:  1, // CET user state, supported
+		xss_cet_p			:  1, // CET supervisor state, supported
+		xss_hdc				:  1, // HDC state, supported
+		xss_uintr			:  1, // UINTR state, supported
+		xss_lbr				:  1, // LBR state, supported
+		xss_hwp				:  1, // HWP state, supported
+						: 15; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0xd_2 {
+	// eax
+	u32	xsave_sz			: 32; // Size of save area for subleaf-N feature, in bytes
+	// ebx
+	u32	xsave_offset			: 32; // Offset of save area for subleaf-N feature, in bytes
+	// ecx
+	u32	is_xss_bit			:  1, // Subleaf N describes an XSS bit, otherwise XCR0 bit
+		compacted_xsave_64byte_aligned	:  1, // When compacted, subleaf-N feature XSAVE area is 64-byte aligned
+						: 30; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0xf
+ * Intel RDT / AMD PQoS resource monitoring
+ */
+
+struct leaf_0xf_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32	core_rmid_max			: 32; // RMID max, within this core, all types (0-based)
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					:  1, // Reserved
+		llc_qos_mon			:  1, // LLC QoS-monitoring supported
+						: 30; // Reserved
+};
+
+struct leaf_0xf_1 {
+	// eax
+	u32	l3c_qm_bitwidth			:  8, // L3 QoS-monitoring counter bitwidth (24-based)
+		l3c_qm_overflow_bit		:  1, // QM_CTR MSR bit 61 is an overflow bit
+						: 23; // Reserved
+	// ebx
+	u32	l3c_qm_conver_factor		: 32; // QM_CTR MSR conversion factor to bytes
+	// ecx
+	u32	l3c_qm_rmid_max			: 32; // L3 QoS-monitoring max RMID
+	// edx
+	u32	l3c_qm_occupancy		:  1, // L3 QoS occupancy monitoring supported
+		l3c_qm_mbm_total		:  1, // L3 QoS total bandwidth monitoring supported
+		l3c_qm_mbm_local		:  1, // L3 QoS local bandwidth monitoring supported
+						: 29; // Reserved
+};
+
+/*
+ * Leaf 0x10
+ * Intel RDT / AMD PQoS allocation enumeration
+ */
+
+struct leaf_0x10_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32					:  1, // Reserved
+		cat_l3				:  1, // L3 Cache Allocation Technology supported
+		cat_l2				:  1, // L2 Cache Allocation Technology supported
+		mba				:  1, // Memory Bandwidth Allocation supported
+						: 28; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x10_1 {
+	// eax
+	u32	cat_cbm_len			:  5, // L3/L2_CAT capacity bitmask length, minus-one notation
+						: 27; // Reserved
+	// ebx
+	u32	cat_units_bitmap		: 32; // L3/L2_CAT bitmap of allocation units
+	// ecx
+	u32					:  1, // Reserved
+		l3_cat_cos_infreq_updates	:  1, // L3_CAT COS updates should be infrequent
+		cat_cdp_supported		:  1, // L3/L2_CAT CDP (Code and Data Prioritization)
+		cat_sparse_1s			:  1, // L3/L2_CAT non-contiguous 1s value supported
+						: 28; // Reserved
+	// edx
+	u32	cat_cos_max			: 16, // L3/L2_CAT max COS (Class of Service) supported
+						: 16; // Reserved
+};
+
+struct leaf_0x10_3 {
+	// eax
+	u32	mba_max_delay			: 12, // Max MBA throttling value; minus-one notation
+						: 20; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32	mba_per_thread			:  1, // Per-thread MBA controls are supported
+						:  1, // Reserved
+		mba_delay_linear		:  1, // Delay values are linear
+						: 29; // Reserved
+	// edx
+	u32	mba_cos_max			: 16, // MBA max Class of Service supported
+						: 16; // Reserved
+};
+
+/*
+ * Leaf 0x12
+ * Intel Software Guard Extensions (SGX) enumeration
+ */
+
+struct leaf_0x12_0 {
+	// eax
+	u32	sgx1				:  1, // SGX1 leaf functions supported
+		sgx2				:  1, // SGX2 leaf functions supported
+						:  3, // Reserved
+		enclv_leaves			:  1, // ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported
+		encls_leaves			:  1, // ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported
+		enclu_everifyreport2		:  1, // ENCLU leaf EVERIFYREPORT2 supported
+						:  2, // Reserved
+		encls_eupdatesvn		:  1, // ENCLS leaf EUPDATESVN supported
+		enclu_edeccssa			:  1, // ENCLU leaf EDECCSSA supported
+						: 20; // Reserved
+	// ebx
+	u32	miscselect_exinfo		:  1, // SSA.MISC frame: reporting #PF and #GP exceptions inside enclave supported
+		miscselect_cpinfo		:  1, // SSA.MISC frame: reporting #CP exceptions inside enclave supported
+						: 30; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	max_enclave_sz_not64		:  8, // Maximum enclave size in non-64-bit mode (log2)
+		max_enclave_sz_64		:  8, // Maximum enclave size in 64-bit mode (log2)
+						: 16; // Reserved
+};
+
+struct leaf_0x12_1 {
+	// eax
+	u32	secs_attr_init			:  1, // ATTRIBUTES.INIT supported (enclave initialized by EINIT)
+		secs_attr_debug			:  1, // ATTRIBUTES.DEBUG supported (enclave permits debugger read/write)
+		secs_attr_mode64bit		:  1, // ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)
+						:  1, // Reserved
+		secs_attr_provisionkey		:  1, // ATTRIBUTES.PROVISIONKEY supported (provisioning key available)
+		secs_attr_einittoken_key	:  1, // ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available)
+		secs_attr_cet			:  1, // ATTRIBUTES.CET supported (enable CET attributes)
+		secs_attr_kss			:  1, // ATTRIBUTES.KSS supported (Key Separation and Sharing enabled)
+						:  2, // Reserved
+		secs_attr_aexnotify		:  1, // ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications
+						: 21; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32	xfrm_x87			:  1, // Enclave XFRM.X87 (bit 0) supported
+		xfrm_sse			:  1, // Enclave XFRM.SEE (bit 1) supported
+		xfrm_avx			:  1, // Enclave XFRM.AVX (bit 2) supported
+		xfrm_mpx_bndregs		:  1, // Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers)
+		xfrm_mpx_bndcsr			:  1, // Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers)
+		xfrm_avx512_opmask		:  1, // Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers)
+		xfrm_avx512_zmm_hi256		:  1, // Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers)
+		xfrm_avx512_hi16_zmm		:  1, // Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers)
+						:  1, // Reserved
+		xfrm_pkru			:  1, // Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU registers)
+						:  7, // Reserved
+		xfrm_tileconfig			:  1, // Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
+		xfrm_tiledata			:  1, // Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
+						: 13; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x12_2 {
+	// eax
+	u32	subleaf_type			:  4, // Subleaf type (dictates output layout)
+						:  8, // Reserved
+		epc_sec_base_addr_0		: 20; // EPC section base address, bits[12:31]
+	// ebx
+	u32	epc_sec_base_addr_1		: 20, // EPC section base address, bits[32:51]
+						: 12; // Reserved
+	// ecx
+	u32	epc_sec_type			:  4, // EPC section type / property encoding
+						:  8, // Reserved
+		epc_sec_size_0			: 20; // EPC section size, bits[12:31]
+	// edx
+	u32	epc_sec_size_1			: 20, // EPC section size, bits[32:51]
+						: 12; // Reserved
+};
+
+/*
+ * Leaf 0x14
+ * Intel Processor Trace enumeration
+ */
+
+struct leaf_0x14_0 {
+	// eax
+	u32	pt_max_subleaf			: 32; // Maximum leaf 0x14 subleaf
+	// ebx
+	u32	cr3_filtering			:  1, // IA32_RTIT_CR3_MATCH is accessible
+		psb_cyc				:  1, // Configurable PSB and cycle-accurate mode
+		ip_filtering			:  1, // IP/TraceStop filtering; Warm-reset PT MSRs preservation
+		mtc_timing			:  1, // MTC timing packet; COFI-based packets suppression
+		ptwrite				:  1, // PTWRITE support
+		power_event_trace		:  1, // Power Event Trace support
+		psb_pmi_preserve		:  1, // PSB and PMI preservation support
+		event_trace			:  1, // Event Trace packet generation through IA32_RTIT_CTL.EventEn
+		tnt_disable			:  1, // TNT packet generation disable through IA32_RTIT_CTL.DisTNT
+						: 23; // Reserved
+	// ecx
+	u32	topa_output			:  1, // ToPA output scheme support
+		topa_multiple_entries		:  1, // ToPA tables can hold multiple entries
+		single_range_output		:  1, // Single-range output scheme supported
+		trance_transport_output		:  1, // Trace Transport subsystem output support
+						: 27, // Reserved
+		ip_payloads_lip			:  1; // IP payloads have LIP values (CS base included)
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x14_1 {
+	// eax
+	u32	num_address_ranges		:  3, // Filtering number of configurable Address Ranges
+						: 13, // Reserved
+		mtc_periods_bmp			: 16; // Bitmap of supported MTC period encodings
+	// ebx
+	u32	cycle_thresholds_bmp		: 16, // Bitmap of supported Cycle Threshold encodings
+		psb_periods_bmp			: 16; // Bitmap of supported Configurable PSB frequency encodings
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x15
+ * Intel TSC (Time Stamp Counter) enumeration
+ */
+
+struct leaf_0x15_0 {
+	// eax
+	u32	tsc_denominator			: 32; // Denominator of the TSC/'core crystal clock' ratio
+	// ebx
+	u32	tsc_numerator			: 32; // Numerator of the TSC/'core crystal clock' ratio
+	// ecx
+	u32	cpu_crystal_hz			: 32; // Core crystal clock nominal frequency, in Hz
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x16
+ * Intel processor frequency enumeration
+ */
+
+struct leaf_0x16_0 {
+	// eax
+	u32	cpu_base_mhz			: 16, // Processor base frequency, in MHz
+						: 16; // Reserved
+	// ebx
+	u32	cpu_max_mhz			: 16, // Processor max frequency, in MHz
+						: 16; // Reserved
+	// ecx
+	u32	bus_mhz				: 16, // Bus reference frequency, in MHz
+						: 16; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x17
+ * Intel SoC vendor attributes enumeration
+ */
+
+struct leaf_0x17_0 {
+	// eax
+	u32	soc_max_subleaf			: 32; // Maximum leaf 0x17 subleaf
+	// ebx
+	u32	soc_vendor_id			: 16, // SoC vendor ID
+		is_vendor_scheme		:  1, // Assigned by industry enumeration scheme (not Intel)
+						: 15; // Reserved
+	// ecx
+	u32	soc_proj_id			: 32; // SoC project ID, assigned by vendor
+	// edx
+	u32	soc_stepping_id			: 32; // Soc project stepping ID, assigned by vendor
+};
+
+struct leaf_0x17_1 {
+	// eax
+	u32	vendor_brand_a			: 32; // Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
+	// ebx
+	u32	vendor_brand_b			: 32; // Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
+	// ecx
+	u32	vendor_brand_c			: 32; // Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
+	// edx
+	u32	vendor_brand_d			: 32; // Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)
+};
+
+/*
+ * Leaf 0x18
+ * Intel determenestic address translation (TLB) parameters
+ */
+
+struct leaf_0x18_0 {
+	// eax
+	u32	tlb_max_subleaf			: 32; // Maximum leaf 0x18 subleaf
+	// ebx
+	u32	tlb_4k_page			:  1, // TLB 4KB-page entries supported
+		tlb_2m_page			:  1, // TLB 2MB-page entries supported
+		tlb_4m_page			:  1, // TLB 4MB-page entries supported
+		tlb_1g_page			:  1, // TLB 1GB-page entries supported
+						:  4, // Reserved
+		hard_partitioning		:  3, // (Hard/Soft) partitioning between logical CPUs sharing this structure
+						:  5, // Reserved
+		n_way_associative		: 16; // Ways of associativity
+	// ecx
+	u32	n_sets				: 32; // Number of sets
+	// edx
+	u32	tlb_type			:  5, // Translation cache type (TLB type)
+		tlb_cache_level			:  3, // Translation cache level (1-based)
+		is_fully_associative		:  1, // Fully-associative structure
+						:  5, // Reserved
+		tlb_max_addressible_ids		: 12, // Max number of addressable IDs for logical CPUs sharing this TLB - 1
+						:  6; // Reserved
+};
+
+/*
+ * Leaf 0x19
+ * Intel Key Locker enumeration
+ */
+
+struct leaf_0x19_0 {
+	// eax
+	u32	kl_cpl0_only			:  1, // CPL0-only key Locker restriction supported
+		kl_no_encrypt			:  1, // No-encrypt key locker restriction supported
+		kl_no_decrypt			:  1, // No-decrypt key locker restriction supported
+						: 29; // Reserved
+	// ebx
+	u32	aes_keylocker			:  1, // AES key locker instructions supported
+						:  1, // Reserved
+		aes_keylocker_wide		:  1, // AES wide key locker instructions supported
+						:  1, // Reserved
+		kl_msr_iwkey			:  1, // Key locker MSRs and IWKEY backups supported
+						: 27; // Reserved
+	// ecx
+	u32	loadiwkey_no_backup		:  1, // LOADIWKEY NoBackup parameter supported
+		iwkey_rand			:  1, // IWKEY randomization (KeySource encoding 1) supported
+						: 30; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x1a
+ * Intel hybrid CPUs identification (e.g. Atom, Core)
+ */
+
+struct leaf_0x1a_0 {
+	// eax
+	u32	core_native_model		: 24, // This core's native model ID
+		core_type			:  8; // This core's type
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x1b
+ * Intel PCONFIG (Platform configuration) enumeration
+ */
+
+struct leaf_0x1b_0 {
+	// eax
+	u32	pconfig_subleaf_type		: 12, // CPUID 0x1b subleaf type
+						: 20; // Reserved
+	// ebx
+	u32	pconfig_target_id_x		: 32; // A supported PCONFIG target ID
+	// ecx
+	u32	pconfig_target_id_y		: 32; // A supported PCONFIG target ID
+	// edx
+	u32	pconfig_target_id_z		: 32; // A supported PCONFIG target ID
+};
+
+/*
+ * Leaf 0x1c
+ * Intel LBR (Last Branch Record) enumeration
+ */
+
+struct leaf_0x1c_0 {
+	// eax
+	u32	lbr_depth_8			:  1, // Max stack depth (number of LBR entries) = 8
+		lbr_depth_16			:  1, // Max stack depth (number of LBR entries) = 16
+		lbr_depth_24			:  1, // Max stack depth (number of LBR entries) = 24
+		lbr_depth_32			:  1, // Max stack depth (number of LBR entries) = 32
+		lbr_depth_40			:  1, // Max stack depth (number of LBR entries) = 40
+		lbr_depth_48			:  1, // Max stack depth (number of LBR entries) = 48
+		lbr_depth_56			:  1, // Max stack depth (number of LBR entries) = 56
+		lbr_depth_64			:  1, // Max stack depth (number of LBR entries) = 64
+						: 22, // Reserved
+		lbr_deep_c_reset		:  1, // LBRs maybe cleared on MWAIT C-state > C1
+		lbr_ip_is_lip			:  1; // LBR IP contain Last IP, otherwise effective IP
+	// ebx
+	u32	lbr_cpl				:  1, // CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported
+		lbr_branch_filter		:  1, // Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported
+		lbr_call_stack			:  1, // Call-stack mode (IA32_LBR_CTL[3] = 1) supported
+						: 29; // Reserved
+	// ecx
+	u32	lbr_mispredict			:  1, // Branch misprediction bit supported (IA32_LBR_x_INFO[63])
+		lbr_timed_lbr			:  1, // Timed LBRs (CPU cycles since last LBR entry) supported
+		lbr_branch_type			:  1, // Branch type field (IA32_LBR_INFO_x[59:56]) supported
+						: 13, // Reserved
+		lbr_events_gpc_bmp		:  4, // LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters
+						: 12; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x1d
+ * Intel AMX (Advanced Matrix Extensions) tile information
+ */
+
+struct leaf_0x1d_0 {
+	// eax
+	u32	amx_max_palette			: 32; // Highest palette ID / subleaf ID
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x1d_1 {
+	// eax
+	u32	amx_palette_size		: 16, // AMX palette total tiles size, in bytes
+		amx_tile_size			: 16; // AMX single tile's size, in bytes
+	// ebx
+	u32	amx_tile_row_size		: 16, // AMX tile single row's size, in bytes
+		amx_palette_nr_tiles		: 16; // AMX palette number of tiles
+	// ecx
+	u32	amx_tile_nr_rows		: 16, // AMX tile max number of rows
+						: 16; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x1e
+ * Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
+ */
+
+struct leaf_0x1e_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32	tmul_maxk			:  8, // TMUL unit maximum height, K (rows or columns)
+		tmul_maxn			: 16, // TMUL unit maximum SIMD dimension, N (column bytes)
+						:  8; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x1f
+ * Intel extended topology enumeration v2
+ */
+
+struct leaf_0x1f_0 {
+	// eax
+	u32	x2apic_id_shift			:  5, // Bit width of this level (previous levels inclusive)
+						: 27; // Reserved
+	// ebx
+	u32	domain_lcpus_count		: 16, // Logical CPUs count across all instances of this domain
+						: 16; // Reserved
+	// ecx
+	u32	domain_level			:  8, // This domain level (subleaf ID)
+		domain_type			:  8, // This domain type
+						: 16; // Reserved
+	// edx
+	u32	x2apic_id			: 32; // x2APIC ID of current logical CPU
+};
+
+/*
+ * Leaf 0x20
+ * Intel HRESET (History Reset) enumeration
+ */
+
+struct leaf_0x20_0 {
+	// eax
+	u32	hreset_nr_subleaves		: 32; // CPUID 0x20 max subleaf + 1
+	// ebx
+	u32	hreset_thread_director		:  1, // HRESET of Intel thread director is supported
+						: 31; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x21
+ * Intel TD (Trust Domain) guest execution environment enumeration
+ */
+
+struct leaf_0x21_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32	tdx_vendorid_0			: 32; // TDX vendor ID string bytes 0 - 3
+	// ecx
+	u32	tdx_vendorid_2			: 32; // CPU vendor ID string bytes 8 - 11
+	// edx
+	u32	tdx_vendorid_1			: 32; // CPU vendor ID string bytes 4 - 7
+};
+
+/*
+ * Leaf 0x23
+ * Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)
+ */
+
+struct leaf_0x23_0 {
+	// eax
+	u32					:  1, // Reserved
+		subleaf_1_counters		:  1, // Subleaf 1, PMU counters bitmaps, is valid
+						:  1, // Reserved
+		subleaf_3_events		:  1, // Subleaf 3, PMU events bitmaps, is valid
+						: 28; // Reserved
+	// ebx
+	u32	unitmask2			:  1, // IA32_PERFEVTSELx MSRs UnitMask2 is supported
+		zbit				:  1, // IA32_PERFEVTSELx MSRs Z-bit is supported
+						: 30; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x23_1 {
+	// eax
+	u32	pmu_gp_counters_bitmap		: 32; // General-purpose PMU counters bitmap
+	// ebx
+	u32	pmu_f_counters_bitmap		: 32; // Fixed PMU counters bitmap
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x23_3 {
+	// eax
+	u32	core_cycles_evt			:  1, // Core cycles event supported
+		insn_retired_evt		:  1, // Instructions retired event supported
+		ref_cycles_evt			:  1, // Reference cycles event supported
+		llc_refs_evt			:  1, // Last-level cache references event supported
+		llc_misses_evt			:  1, // Last-level cache misses event supported
+		br_insn_ret_evt			:  1, // Branch instruction retired event supported
+		br_mispr_evt			:  1, // Branch mispredict retired event supported
+		td_slots_evt			:  1, // Topdown slots event supported
+		td_backend_bound_evt		:  1, // Topdown backend bound event supported
+		td_bad_spec_evt			:  1, // Topdown bad speculation event supported
+		td_frontend_bound_evt		:  1, // Topdown frontend bound event supported
+		td_retiring_evt			:  1, // Topdown retiring event support
+						: 20; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x40000000
+ * Maximum hypervisor standard leaf + hypervisor vendor string
+ */
+
+struct leaf_0x40000000_0 {
+	// eax
+	u32	max_hyp_leaf			: 32; // Maximum hypervisor standard leaf number
+	// ebx
+	u32	hypervisor_id_0			: 32; // Hypervisor ID string bytes 0 - 3
+	// ecx
+	u32	hypervisor_id_1			: 32; // Hypervisor ID string bytes 4 - 7
+	// edx
+	u32	hypervisor_id_2			: 32; // Hypervisor ID string bytes 8 - 11
+};
+
+/*
+ * Leaf 0x80000000
+ * Maximum extended leaf number + AMD/Transmeta CPU vendor string
+ */
+
+struct leaf_0x80000000_0 {
+	// eax
+	u32	max_ext_leaf			: 32; // Maximum extended CPUID leaf supported
+	// ebx
+	u32	cpu_vendorid_0			: 32; // Vendor ID string bytes 0 - 3
+	// ecx
+	u32	cpu_vendorid_2			: 32; // Vendor ID string bytes 8 - 11
+	// edx
+	u32	cpu_vendorid_1			: 32; // Vendor ID string bytes 4 - 7
+};
+
+/*
+ * Leaf 0x80000001
+ * Extended CPU feature identifiers
+ */
+
+struct leaf_0x80000001_0 {
+	// eax
+	u32	e_stepping_id			:  4, // Stepping ID
+		e_base_model			:  4, // Base processor model
+		e_base_family			:  4, // Base processor family
+		e_base_type			:  2, // Base processor type (Transmeta)
+						:  2, // Reserved
+		e_ext_model			:  4, // Extended processor model
+		e_ext_family			:  8, // Extended processor family
+						:  4; // Reserved
+	// ebx
+	u32	brand_id			: 16, // Brand ID
+						: 12, // Reserved
+		pkg_type			:  4; // Package type
+	// ecx
+	u32	lahf_lm				:  1, // LAHF and SAHF in 64-bit mode
+		cmp_legacy			:  1, // Multi-processing legacy mode (No HT)
+		svm				:  1, // Secure Virtual Machine
+		extapic				:  1, // Extended APIC space
+		cr8_legacy			:  1, // LOCK MOV CR0 means MOV CR8
+		lzcnt_abm			:  1, // LZCNT advanced bit manipulation
+		sse4a				:  1, // SSE4A support
+		misaligned_sse			:  1, // Misaligned SSE mode
+		_3dnow_prefetch			:  1, // 3DNow PREFETCH/PREFETCHW support
+		osvw				:  1, // OS visible workaround
+		ibs				:  1, // Instruction based sampling
+		xop				:  1, // XOP: extended operation (AVX instructions)
+		skinit				:  1, // SKINIT/STGI support
+		wdt				:  1, // Watchdog timer support
+						:  1, // Reserved
+		lwp				:  1, // Lightweight profiling
+		fma4				:  1, // 4-operand FMA instruction
+		tce				:  1, // Translation cache extension
+						:  1, // Reserved
+		nodeid_msr			:  1, // NodeId MSR (0xc001100c)
+						:  1, // Reserved
+		tbm				:  1, // Trailing bit manipulations
+		topoext				:  1, // Topology Extensions (leaf 0x8000001d)
+		perfctr_core			:  1, // Core performance counter extensions
+		perfctr_nb			:  1, // NB/DF performance counter extensions
+						:  1, // Reserved
+		data_bp_ext			:  1, // Data access breakpoint extension
+		perf_tsc			:  1, // Performance time-stamp counter
+		perfctr_llc			:  1, // LLC (L3) performance counter extensions
+		mwaitx				:  1, // MWAITX/MONITORX support
+		addr_mask_ext			:  1, // Breakpoint address mask extension (to bit 31)
+						:  1; // Reserved
+	// edx
+	u32	e_fpu				:  1, // Floating-Point Unit on-chip (x87)
+		e_vme				:  1, // Virtual-8086 Mode Extensions
+		e_de				:  1, // Debugging Extensions
+		e_pse				:  1, // Page Size Extension
+		e_tsc				:  1, // Time Stamp Counter
+		e_msr				:  1, // Model-Specific Registers (RDMSR and WRMSR support)
+		pae				:  1, // Physical Address Extensions
+		mce				:  1, // Machine Check Exception
+		cx8				:  1, // CMPXCHG8B instruction
+		apic				:  1, // APIC on-chip
+						:  1, // Reserved
+		syscall				:  1, // SYSCALL and SYSRET instructions
+		mtrr				:  1, // Memory Type Range Registers
+		pge				:  1, // Page Global Extensions
+		mca				:  1, // Machine Check Architecture
+		cmov				:  1, // Conditional Move Instruction
+		pat				:  1, // Page Attribute Table
+		pse36				:  1, // Page Size Extension (36-bit)
+						:  1, // Reserved
+		obsolete_mp_bit			:  1, // Out-of-spec AMD Multiprocessing bit
+		nx				:  1, // No-execute page protection
+						:  1, // Reserved
+		mmxext				:  1, // AMD MMX extensions
+		e_mmx				:  1, // MMX instructions
+		e_fxsr				:  1, // FXSAVE and FXRSTOR instructions
+		fxsr_opt			:  1, // FXSAVE and FXRSTOR optimizations
+		page1gb				:  1, // 1-GB large page support
+		rdtscp				:  1, // RDTSCP instruction
+						:  1, // Reserved
+		lm				:  1, // Long mode (x86-64, 64-bit support)
+		_3dnowext			:  1, // AMD 3DNow extensions
+		_3dnow				:  1; // 3DNow instructions
+};
+
+/*
+ * Leaf 0x80000002
+ * CPU brand ID string, bytes 0 - 15
+ */
+
+struct leaf_0x80000002_0 {
+	// eax
+	u32	cpu_brandid_0			: 32; // CPU brand ID string, bytes 0 - 3
+	// ebx
+	u32	cpu_brandid_1			: 32; // CPU brand ID string, bytes 4 - 7
+	// ecx
+	u32	cpu_brandid_2			: 32; // CPU brand ID string, bytes 8 - 11
+	// edx
+	u32	cpu_brandid_3			: 32; // CPU brand ID string, bytes 12 - 15
+};
+
+/*
+ * Leaf 0x80000003
+ * CPU brand ID string, bytes 16 - 31
+ */
+
+struct leaf_0x80000003_0 {
+	// eax
+	u32	cpu_brandid_4			: 32; // CPU brand ID string bytes, 16 - 19
+	// ebx
+	u32	cpu_brandid_5			: 32; // CPU brand ID string bytes, 20 - 23
+	// ecx
+	u32	cpu_brandid_6			: 32; // CPU brand ID string bytes, 24 - 27
+	// edx
+	u32	cpu_brandid_7			: 32; // CPU brand ID string bytes, 28 - 31
+};
+
+/*
+ * Leaf 0x80000004
+ * CPU brand ID string, bytes 32 - 47
+ */
+
+struct leaf_0x80000004_0 {
+	// eax
+	u32	cpu_brandid_8			: 32; // CPU brand ID string, bytes 32 - 35
+	// ebx
+	u32	cpu_brandid_9			: 32; // CPU brand ID string, bytes 36 - 39
+	// ecx
+	u32	cpu_brandid_10			: 32; // CPU brand ID string, bytes 40 - 43
+	// edx
+	u32	cpu_brandid_11			: 32; // CPU brand ID string, bytes 44 - 47
+};
+
+/*
+ * Leaf 0x80000005
+ * AMD/Transmeta L1 cache and L1 TLB enumeration
+ */
+
+struct leaf_0x80000005_0 {
+	// eax
+	u32	l1_itlb_2m_4m_nentries		:  8, // L1 ITLB #entries, 2M and 4M pages
+		l1_itlb_2m_4m_assoc		:  8, // L1 ITLB associativity, 2M and 4M pages
+		l1_dtlb_2m_4m_nentries		:  8, // L1 DTLB #entries, 2M and 4M pages
+		l1_dtlb_2m_4m_assoc		:  8; // L1 DTLB associativity, 2M and 4M pages
+	// ebx
+	u32	l1_itlb_4k_nentries		:  8, // L1 ITLB #entries, 4K pages
+		l1_itlb_4k_assoc		:  8, // L1 ITLB associativity, 4K pages
+		l1_dtlb_4k_nentries		:  8, // L1 DTLB #entries, 4K pages
+		l1_dtlb_4k_assoc		:  8; // L1 DTLB associativity, 4K pages
+	// ecx
+	u32	l1_dcache_line_size		:  8, // L1 dcache line size, in bytes
+		l1_dcache_nlines		:  8, // L1 dcache lines per tag
+		l1_dcache_assoc			:  8, // L1 dcache associativity
+		l1_dcache_size_kb		:  8; // L1 dcache size, in KB
+	// edx
+	u32	l1_icache_line_size		:  8, // L1 icache line size, in bytes
+		l1_icache_nlines		:  8, // L1 icache lines per tag
+		l1_icache_assoc			:  8, // L1 icache associativity
+		l1_icache_size_kb		:  8; // L1 icache size, in KB
+};
+
+/*
+ * Leaf 0x80000006
+ * (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration
+ */
+
+struct leaf_0x80000006_0 {
+	// eax
+	u32	l2_itlb_2m_4m_nentries		: 12, // L2 iTLB #entries, 2M and 4M pages
+		l2_itlb_2m_4m_assoc		:  4, // L2 iTLB associativity, 2M and 4M pages
+		l2_dtlb_2m_4m_nentries		: 12, // L2 dTLB #entries, 2M and 4M pages
+		l2_dtlb_2m_4m_assoc		:  4; // L2 dTLB associativity, 2M and 4M pages
+	// ebx
+	u32	l2_itlb_4k_nentries		: 12, // L2 iTLB #entries, 4K pages
+		l2_itlb_4k_assoc		:  4, // L2 iTLB associativity, 4K pages
+		l2_dtlb_4k_nentries		: 12, // L2 dTLB #entries, 4K pages
+		l2_dtlb_4k_assoc		:  4; // L2 dTLB associativity, 4K pages
+	// ecx
+	u32	l2_line_size			:  8, // L2 cache line size, in bytes
+		l2_nlines			:  4, // L2 cache number of lines per tag
+		l2_assoc			:  4, // L2 cache associativity
+		l2_size_kb			: 16; // L2 cache size, in KB
+	// edx
+	u32	l3_line_size			:  8, // L3 cache line size, in bytes
+		l3_nlines			:  4, // L3 cache number of lines per tag
+		l3_assoc			:  4, // L3 cache associativity
+						:  2, // Reserved
+		l3_size_range			: 14; // L3 cache size range
+};
+
+/*
+ * Leaf 0x80000007
+ * CPU power management (mostly AMD) and AMD RAS enumeration
+ */
+
+struct leaf_0x80000007_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32	mca_overflow_recovery		:  1, // MCA overflow conditions not fatal
+		succor				:  1, // Software containment of uncorrectable errors
+		hw_assert			:  1, // Hardware assert MSRs
+		scalable_mca			:  1, // Scalable MCA (MCAX MSRs)
+						: 28; // Reserved
+	// ecx
+	u32	cpu_pwr_sample_ratio		: 32; // CPU power sample time ratio
+	// edx
+	u32	digital_temp			:  1, // Digital temperature sensor
+		powernow_freq_id		:  1, // PowerNOW! frequency scaling
+		powernow_volt_id		:  1, // PowerNOW! voltage scaling
+		thermal_trip			:  1, // THERMTRIP (Thermal Trip)
+		hw_thermal_control		:  1, // Hardware thermal control
+		sw_thermal_control		:  1, // Software thermal control
+		_100mhz_steps			:  1, // 100 MHz multiplier control
+		hw_pstate			:  1, // Hardware P-state control
+		constant_tsc			:  1, // TSC ticks at constant rate across all P and C states
+		core_perf_boost			:  1, // Core performance boost
+		eff_freq_ro			:  1, // Read-only effective frequency interface
+		proc_feedback			:  1, // Processor feedback interface (deprecated)
+		proc_power_reporting		:  1, // Processor power reporting interface
+		connected_standby		:  1, // CPU Connected Standby support
+		rapl_interface			:  1, // Runtime Average Power Limit interface
+						: 17; // Reserved
+};
+
+/*
+ * Leaf 0x80000008
+ * CPU capacity parameters and extended feature flags (mostly AMD)
+ */
+
+struct leaf_0x80000008_0 {
+	// eax
+	u32	phys_addr_bits			:  8, // Max physical address bits
+		virt_addr_bits			:  8, // Max virtual address bits
+		guest_phys_addr_bits		:  8, // Max nested-paging guest physical address bits
+						:  8; // Reserved
+	// ebx
+	u32	clzero				:  1, // CLZERO supported
+		insn_retired_perf		:  1, // Instruction retired counter MSR
+		xsave_err_ptr			:  1, // XSAVE/XRSTOR always saves/restores FPU error pointers
+		invlpgb				:  1, // INVLPGB broadcasts a TLB invalidate to all threads
+		rdpru				:  1, // RDPRU (Read Processor Register at User level) supported
+						:  1, // Reserved
+		mba				:  1, // Memory Bandwidth Allocation (AMD bit)
+						:  1, // Reserved
+		mcommit				:  1, // MCOMMIT (Memory commit) supported
+		wbnoinvd			:  1, // WBNOINVD supported
+						:  2, // Reserved
+		ibpb				:  1, // Indirect Branch Prediction Barrier
+		wbinvd_int			:  1, // Interruptible WBINVD/WBNOINVD
+		ibrs				:  1, // Indirect Branch Restricted Speculation
+		stibp				:  1, // Single Thread Indirect Branch Prediction mode
+		ibrs_always_on			:  1, // IBRS always-on preferred
+		stibp_always_on			:  1, // STIBP always-on preferred
+		ibrs_fast			:  1, // IBRS is preferred over software solution
+		ibrs_same_mode			:  1, // IBRS provides same mode protection
+		no_efer_lmsle			:  1, // EFER[LMSLE] bit (Long-Mode Segment Limit Enable) unsupported
+		tlb_flush_nested		:  1, // INVLPGB RAX[5] bit can be set (nested translations)
+						:  1, // Reserved
+		amd_ppin			:  1, // Protected Processor Inventory Number
+		amd_ssbd			:  1, // Speculative Store Bypass Disable
+		virt_ssbd			:  1, // virtualized SSBD (Speculative Store Bypass Disable)
+		amd_ssb_no			:  1, // SSBD is not needed (fixed in hardware)
+		cppc				:  1, // Collaborative Processor Performance Control
+		amd_psfd			:  1, // Predictive Store Forward Disable
+		btc_no				:  1, // CPU not affected by Branch Type Confusion
+		ibpb_ret			:  1, // IBPB clears RSB/RAS too
+		branch_sampling			:  1; // Branch Sampling supported
+	// ecx
+	u32	cpu_nthreads			:  8, // Number of physical threads - 1
+						:  4, // Reserved
+		apicid_coreid_len		:  4, // Number of thread core ID bits (shift) in APIC ID
+		perf_tsc_len			:  2, // Performance time-stamp counter size
+						: 14; // Reserved
+	// edx
+	u32	invlpgb_max_pages		: 16, // INVLPGB maximum page count
+		rdpru_max_reg_id		: 16; // RDPRU max register ID (ECX input)
+};
+
+/*
+ * Leaf 0x8000000a
+ * AMD SVM (Secure Virtual Machine) enumeration
+ */
+
+struct leaf_0x8000000a_0 {
+	// eax
+	u32	svm_version			:  8, // SVM revision number
+						: 24; // Reserved
+	// ebx
+	u32	svm_nasid			: 32; // Number of address space identifiers (ASID)
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	nested_pt			:  1, // Nested paging
+		lbr_virt			:  1, // LBR virtualization
+		svm_lock			:  1, // SVM lock
+		nrip_save			:  1, // NRIP save support on #VMEXIT
+		tsc_rate_msr			:  1, // MSR based TSC rate control
+		vmcb_clean			:  1, // VMCB clean bits support
+		flush_by_asid			:  1, // Flush by ASID + Extended VMCB TLB_Control
+		decode_assists			:  1, // Decode Assists support
+						:  2, // Reserved
+		pause_filter			:  1, // Pause intercept filter
+						:  1, // Reserved
+		pf_threshold			:  1, // Pause filter threshold
+		avic				:  1, // Advanced virtual interrupt controller
+						:  1, // Reserved
+		v_vmsave_vmload			:  1, // Virtual VMSAVE/VMLOAD (nested virtualization)
+		v_gif				:  1, // Virtualize the Global Interrupt Flag
+		gmet				:  1, // Guest mode execution trap
+		x2avic				:  1, // Virtual x2APIC
+		sss_check			:  1, // Supervisor Shadow Stack restrictions
+		v_spec_ctrl			:  1, // Virtual SPEC_CTRL
+		ro_gpt				:  1, // Read-Only guest page table support
+						:  1, // Reserved
+		h_mce_override			:  1, // Host MCE override
+		tlbsync_int			:  1, // TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB
+		nmi_virt			:  1, // NMI virtualization
+		ibs_virt			:  1, // IBS Virtualization
+		ext_lvt_off_chg			:  1, // Extended LVT offset fault change
+		svme_addr_chk			:  1, // Guest SVME address check
+						:  3; // Reserved
+};
+
+/*
+ * Leaf 0x80000019
+ * AMD TLB 1G-pages enumeration
+ */
+
+struct leaf_0x80000019_0 {
+	// eax
+	u32	l1_itlb_1g_nentries		: 12, // L1 iTLB #entries, 1G pages
+		l1_itlb_1g_assoc		:  4, // L1 iTLB associativity, 1G pages
+		l1_dtlb_1g_nentries		: 12, // L1 dTLB #entries, 1G pages
+		l1_dtlb_1g_assoc		:  4; // L1 dTLB associativity, 1G pages
+	// ebx
+	u32	l2_itlb_1g_nentries		: 12, // L2 iTLB #entries, 1G pages
+		l2_itlb_1g_assoc		:  4, // L2 iTLB associativity, 1G pages
+		l2_dtlb_1g_nentries		: 12, // L2 dTLB #entries, 1G pages
+		l2_dtlb_1g_assoc		:  4; // L2 dTLB associativity, 1G pages
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x8000001a
+ * AMD instruction optimizations enumeration
+ */
+
+struct leaf_0x8000001a_0 {
+	// eax
+	u32	fp_128				:  1, // Internal FP/SIMD exec data path is 128-bits wide
+		movu_preferred			:  1, // SSE: MOVU* better than MOVL*/MOVH*
+		fp_256				:  1, // internal FP/SSE exec data path is 256-bits wide
+						: 29; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x8000001b
+ * AMD IBS (Instruction-Based Sampling) enumeration
+ */
+
+struct leaf_0x8000001b_0 {
+	// eax
+	u32	ibs_flags_valid			:  1, // IBS feature flags valid
+		ibs_fetch_sampling		:  1, // IBS fetch sampling supported
+		ibs_op_sampling			:  1, // IBS execution sampling supported
+		ibs_rdwr_op_counter		:  1, // IBS read/write of op counter supported
+		ibs_op_count			:  1, // IBS OP counting mode supported
+		ibs_branch_target		:  1, // IBS branch target address reporting supported
+		ibs_op_counters_ext		:  1, // IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits
+		ibs_rip_invalid_chk		:  1, // IBS invalid RIP indication supported
+		ibs_op_branch_fuse		:  1, // IBS fused branch micro-op indication supported
+		ibs_fetch_ctl_ext		:  1, // IBS Fetch Control Extended MSR (0xc001103c) supported
+		ibs_op_data_4			:  1, // IBS op data 4 MSR supported
+		ibs_l3_miss_filter		:  1, // IBS L3-miss filtering supported (Zen4+)
+						: 20; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x8000001c
+ * AMD LWP (Lightweight Profiling)
+ */
+
+struct leaf_0x8000001c_0 {
+	// eax
+	u32	os_lwp_avail			:  1, // LWP is available to application programs (supported by OS)
+		os_lpwval			:  1, // LWPVAL instruction is supported by OS
+		os_lwp_ire			:  1, // Instructions Retired Event is supported by OS
+		os_lwp_bre			:  1, // Branch Retired Event is supported by OS
+		os_lwp_dme			:  1, // Dcache Miss Event is supported by OS
+		os_lwp_cnh			:  1, // CPU Clocks Not Halted event is supported by OS
+		os_lwp_rnh			:  1, // CPU Reference clocks Not Halted event is supported by OS
+						: 22, // Reserved
+		os_lwp_cont			:  1, // LWP sampling in continuous mode is supported by OS
+		os_lwp_ptsc			:  1, // Performance Time Stamp Counter in event records is supported by OS
+		os_lwp_int			:  1; // Interrupt on threshold overflow is supported by OS
+	// ebx
+	u32	lwp_lwpcb_sz			:  8, // LWP Control Block size, in quadwords
+		lwp_event_sz			:  8, // LWP event record size, in bytes
+		lwp_max_events			:  8, // LWP max supported EventID value (EventID 255 not included)
+		lwp_event_offset		:  8; // LWP events area offset in the LWP Control Block
+	// ecx
+	u32	lwp_latency_max			:  5, // Number of bits in cache latency counters (10 to 31)
+		lwp_data_adddr			:  1, // Cache miss events report the data address of the reference
+		lwp_latency_rnd			:  3, // Amount by which cache latency is rounded
+		lwp_version			:  7, // LWP implementation version
+		lwp_buf_min_sz			:  8, // LWP event ring buffer min size, in units of 32 event records
+						:  4, // Reserved
+		lwp_branch_predict		:  1, // Branches Retired events can be filtered
+		lwp_ip_filtering		:  1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported
+		lwp_cache_levels		:  1, // Cache-related events can be filtered by cache level
+		lwp_cache_latency		:  1; // Cache-related events can be filtered by latency
+	// edx
+	u32	hw_lwp_avail			:  1, // LWP is available in hardware
+		hw_lpwval			:  1, // LWPVAL instruction is available in hardware
+		hw_lwp_ire			:  1, // Instructions Retired Event is available in hardware
+		hw_lwp_bre			:  1, // Branch Retired Event is available in hardware
+		hw_lwp_dme			:  1, // Dcache Miss Event is available in hardware
+		hw_lwp_cnh			:  1, // Clocks Not Halted event is available in hardware
+		hw_lwp_rnh			:  1, // Reference clocks Not Halted event is available in hardware
+						: 22, // Reserved
+		hw_lwp_cont			:  1, // LWP sampling in continuous mode is available in hardware
+		hw_lwp_ptsc			:  1, // Performance Time Stamp Counter in event records is available in hardware
+		hw_lwp_int			:  1; // Interrupt on threshold overflow is available in hardware
+};
+
+/*
+ * Leaf 0x8000001d
+ * AMD deterministic cache parameters
+ */
+
+struct leaf_0x8000001d_0 {
+	// eax
+	u32	cache_type			:  5, // Cache type field
+		cache_level			:  3, // Cache level (1-based)
+		cache_self_init			:  1, // Self-initializing cache level
+		fully_associative		:  1, // Fully-associative cache
+						:  4, // Reserved
+		num_threads_sharing		: 12, // Number of logical CPUs sharing cache
+						:  6; // Reserved
+	// ebx
+	u32	cache_linesize			: 12, // System coherency line size (0-based)
+		cache_npartitions		: 10, // Physical line partitions (0-based)
+		cache_nways			: 10; // Ways of associativity (0-based)
+	// ecx
+	u32	cache_nsets			: 31, // Cache number of sets (0-based)
+						:  1; // Reserved
+	// edx
+	u32	wbinvd_rll_no_guarantee		:  1, // WBINVD/INVD not guaranteed for Remote Lower-Level caches
+		ll_inclusive			:  1, // Cache is inclusive of Lower-Level caches
+						: 30; // Reserved
+};
+
+/*
+ * Leaf 0x8000001e
+ * AMD CPU topology enumeration
+ */
+
+struct leaf_0x8000001e_0 {
+	// eax
+	u32	ext_apic_id			: 32; // Extended APIC ID
+	// ebx
+	u32	core_id				:  8, // Unique per-socket logical core unit ID
+		core_nthreas			:  8, // #Threads per core (zero-based)
+						: 16; // Reserved
+	// ecx
+	u32	node_id				:  8, // Node (die) ID of invoking logical CPU
+		nnodes_per_socket		:  3, // #nodes in invoking logical CPU's package/socket
+						: 21; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x8000001f
+ * AMD encrypted memory capabilities enumeration (SME/SEV)
+ */
+
+struct leaf_0x8000001f_0 {
+	// eax
+	u32	sme				:  1, // Secure Memory Encryption supported
+		sev				:  1, // Secure Encrypted Virtualization supported
+		vm_page_flush			:  1, // VM Page Flush MSR (0xc001011e) available
+		sev_encrypted_state		:  1, // SEV Encrypted State supported
+		sev_nested_paging		:  1, // SEV secure nested paging supported
+		vm_permission_levels		:  1, // VMPL supported
+		rpmquery			:  1, // RPMQUERY instruction supported
+		vmpl_sss			:  1, // VMPL supervisor shadow stack supported
+		secure_tsc			:  1, // Secure TSC supported
+		virt_tsc_aux			:  1, // Hardware virtualizes TSC_AUX
+		sme_coherent			:  1, // Cache coherency is enforced across encryption domains
+		req_64bit_hypervisor		:  1, // SEV guest mandates 64-bit hypervisor
+		restricted_injection		:  1, // Restricted Injection supported
+		alternate_injection		:  1, // Alternate Injection supported
+		debug_swap			:  1, // SEV-ES: full debug state swap is supported
+		disallow_host_ibs		:  1, // SEV-ES: Disallowing IBS use by the host is supported
+		virt_transparent_enc		:  1, // Virtual Transparent Encryption
+		vmgexit_paremeter		:  1, // VmgexitParameter is supported in SEV_FEATURES
+		virt_tom_msr			:  1, // Virtual TOM MSR is supported
+		virt_ibs			:  1, // IBS state virtualization is supported for SEV-ES guests
+						:  4, // Reserved
+		vmsa_reg_protection		:  1, // VMSA register protection is supported
+		smt_protection			:  1, // SMT protection is supported
+						:  2, // Reserved
+		svsm_page_msr			:  1, // SVSM communication page MSR (0xc001f000) is supported
+		nested_virt_snp_msr		:  1, // VIRT_RMPUPDATE/VIRT_PSMASH MSRs are supported
+						:  2; // Reserved
+	// ebx
+	u32	pte_cbit_pos			:  6, // PTE bit number used to enable memory encryption
+		phys_addr_reduction_nbits	:  6, // Reduction of phys address space when encryption is enabled, in bits
+		vmpl_count			:  4, // Number of VM permission levels (VMPL) supported
+						: 16; // Reserved
+	// ecx
+	u32	enc_guests_max			: 32; // Max supported number of simultaneous encrypted guests
+	// edx
+	u32	min_sev_asid_no_sev_es		: 32; // Minimum ASID for SEV-enabled SEV-ES-disabled guest
+};
+
+/*
+ * Leaf 0x80000020
+ * AMD Platform QoS extended feature IDs
+ */
+
+struct leaf_0x80000020_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32					:  1, // Reserved
+		mba				:  1, // Memory Bandwidth Allocation support
+		smba				:  1, // Slow Memory Bandwidth Allocation support
+		bmec				:  1, // Bandwidth Monitoring Event Configuration support
+		l3rr				:  1, // L3 Range Reservation support
+		abmc				:  1, // Assignable Bandwidth Monitoring Counters
+		sdciae				:  1, // Smart Data Cache Injection (SDCI) Allocation Enforcement
+						: 25; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+struct leaf_0x80000020_1 {
+	// eax
+	u32	mba_limit_len			: 32; // MBA enforcement limit size
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	mba_cos_max			: 32; // MBA max Class of Service number (zero-based)
+};
+
+struct leaf_0x80000020_2 {
+	// eax
+	u32	smba_limit_len			: 32; // SMBA enforcement limit size
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	smba_cos_max			: 32; // SMBA max Class of Service number (zero-based)
+};
+
+struct leaf_0x80000020_3 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32	bmec_num_events			:  8, // BMEC number of bandwidth events available
+						: 24; // Reserved
+	// ecx
+	u32	bmec_local_reads		:  1, // Local NUMA reads can be tracked
+		bmec_remote_reads		:  1, // Remote NUMA reads can be tracked
+		bmec_local_nontemp_wr		:  1, // Local NUMA non-temporal writes can be tracked
+		bmec_remote_nontemp_wr		:  1, // Remote NUMA non-temporal writes can be tracked
+		bmec_local_slow_mem_rd		:  1, // Local NUMA slow-memory reads can be tracked
+		bmec_remote_slow_mem_rd		:  1, // Remote NUMA slow-memory reads can be tracked
+		bmec_all_dirty_victims		:  1, // Dirty QoS victims to all types of memory can be tracked
+						: 25; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x80000021
+ * AMD extended features enumeration 2
+ */
+
+struct leaf_0x80000021_0 {
+	// eax
+	u32	no_nested_data_bp		:  1, // No nested data breakpoints
+		fsgs_non_serializing		:  1, // WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
+		lfence_serializing		:  1, // LFENCE always serializing / synchronizes RDTSC
+		smm_page_cfg_lock		:  1, // SMM paging configuration lock
+						:  2, // Reserved
+		null_sel_clr_base		:  1, // Null selector clears base
+		upper_addr_ignore		:  1, // EFER MSR Upper Address Ignore
+		auto_ibrs			:  1, // EFER MSR Automatic IBRS
+		no_smm_ctl_msr			:  1, // SMM_CTL MSR (0xc0010116) is not available
+		fsrs				:  1, // Fast Short Rep STOSB
+		fsrc				:  1, // Fast Short Rep CMPSB
+						:  1, // Reserved
+		prefetch_ctl_msr		:  1, // Prefetch control MSR is available
+						:  2, // Reserved
+		opcode_reclaim			:  1, // Reserves opcode space
+		user_cpuid_disable		:  1, // #GP when executing CPUID at CPL > 0 is supported
+		epsf				:  1, // Enhanced Predictive Store Forwarding
+						:  3, // Reserved
+		wl_feedback			:  1, // Workload-based heuristic feedback to OS
+						:  1, // Reserved
+		eraps				:  1, // Enhanced Return Address Predictor Security
+						:  2, // Reserved
+		sbpb				:  1, // Selective Branch Predictor Barrier
+		ibpb_brtype			:  1, // Branch predictions flushed from CPU branch predictor
+		srso_no				:  1, // CPU is not subject to the SRSO vulnerability
+		srso_uk_no			:  1, // CPU is not vulnerable to SRSO at user-kernel boundary
+		srso_msr_fix			:  1; // Software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO
+	// ebx
+	u32	microcode_patch_size		: 16, // Size of microcode patch, in 16-byte units
+		rap_size			:  8, // Return Address Predictor size
+						:  8; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x80000022
+ * AMD Performance Monitoring v2 enumeration
+ */
+
+struct leaf_0x80000022_0 {
+	// eax
+	u32	perfmon_v2			:  1, // Performance monitoring v2 supported
+		lbr_v2				:  1, // Last Branch Record v2 extensions (LBR Stack)
+		lbr_pmc_freeze			:  1, // Freezing core performance counters / LBR Stack supported
+						: 29; // Reserved
+	// ebx
+	u32	n_pmc_core			:  4, // Number of core performance counters
+		lbr_v2_stack_size		:  6, // Number of available LBR stack entries
+		n_pmc_northbridge		:  6, // Number of available northbridge (data fabric) performance counters
+		n_pmc_umc			:  6, // Number of available UMC performance counters
+						: 10; // Reserved
+	// ecx
+	u32	active_umc_bitmask		: 32; // Active UMCs bitmask
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x80000023
+ * AMD Secure Multi-key Encryption enumeration
+ */
+
+struct leaf_0x80000023_0 {
+	// eax
+	u32	mem_hmk_mode			:  1, // MEM-HMK encryption mode is supported
+						: 31; // Reserved
+	// ebx
+	u32	mem_hmk_avail_keys		: 16, // MEM-HMK mode: total number of available encryption keys
+						: 16; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x80000026
+ * AMD extended topology enumeration v2
+ */
+
+struct leaf_0x80000026_0 {
+	// eax
+	u32	x2apic_id_shift			:  5, // Bit width of this level (previous levels inclusive)
+						: 24, // Reserved
+		core_has_pwreff_ranking		:  1, // This core has a power efficiency ranking
+		domain_has_hybrid_cores		:  1, // This domain level has hybrid (E, P) cores
+		domain_core_count_asymm		:  1; // The 'Core' domain has asymmetric cores count
+	// ebx
+	u32	domain_lcpus_count		: 16, // Number of logical CPUs at this domain instance
+		core_pwreff_ranking		:  8, // This core's static power efficiency ranking
+		core_native_model_id		:  4, // This core's native model ID
+		core_type			:  4; // This core's type
+	// ecx
+	u32	domain_level			:  8, // This domain level (subleaf ID)
+		domain_type			:  8, // This domain type
+						: 16; // Reserved
+	// edx
+	u32	x2apic_id			: 32; // x2APIC ID of current logical CPU
+};
+
+/*
+ * Leaf 0x80860000
+ * Maximum Transmeta leaf number + CPU vendor ID string
+ */
+
+struct leaf_0x80860000_0 {
+	// eax
+	u32	max_tra_leaf			: 32; // Maximum supported Transmeta leaf number
+	// ebx
+	u32	cpu_vendorid_0			: 32; // Transmeta Vendor ID string bytes 0 - 3
+	// ecx
+	u32	cpu_vendorid_2			: 32; // Transmeta Vendor ID string bytes 8 - 11
+	// edx
+	u32	cpu_vendorid_1			: 32; // Transmeta Vendor ID string bytes 4 - 7
+};
+
+/*
+ * Leaf 0x80860001
+ * Transmeta extended CPU information
+ */
+
+struct leaf_0x80860001_0 {
+	// eax
+	u32	stepping			:  4, // Stepping ID
+		base_model			:  4, // Base CPU model ID
+		base_family_id			:  4, // Base CPU family ID
+		cpu_type			:  2, // CPU type
+						: 18; // Reserved
+	// ebx
+	u32	cpu_rev_mask_minor		:  8, // CPU revision ID, mask minor
+		cpu_rev_mask_major		:  8, // CPU revision ID, mask major
+		cpu_rev_minor			:  8, // CPU revision ID, minor
+		cpu_rev_major			:  8; // CPU revision ID, major
+	// ecx
+	u32	cpu_base_mhz			: 32; // CPU nominal frequency, in MHz
+	// edx
+	u32	recovery			:  1, // Recovery CMS is active (after bad flush)
+		longrun				:  1, // LongRun power management capabilities
+						:  1, // Reserved
+		lrti				:  1, // LongRun Table Interface
+						: 28; // Reserved
+};
+
+/*
+ * Leaf 0x80860002
+ * Transmeta Code Morphing Software (CMS) enumeration
+ */
+
+struct leaf_0x80860002_0 {
+	// eax
+	u32	cpu_rev_id			: 32; // CPU revision ID
+	// ebx
+	u32	cms_rev_mask_2			:  8, // CMS revision ID, mask component 2
+		cms_rev_mask_1			:  8, // CMS revision ID, mask component 1
+		cms_rev_minor			:  8, // CMS revision ID, minor
+		cms_rev_major			:  8; // CMS revision ID, major
+	// ecx
+	u32	cms_rev_mask_3			: 32; // CMS revision ID, mask component 3
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0x80860003
+ * Transmeta CPU information string, bytes 0 - 15
+ */
+
+struct leaf_0x80860003_0 {
+	// eax
+	u32	cpu_info_0			: 32; // CPU info string bytes 0 - 3
+	// ebx
+	u32	cpu_info_1			: 32; // CPU info string bytes 4 - 7
+	// ecx
+	u32	cpu_info_2			: 32; // CPU info string bytes 8 - 11
+	// edx
+	u32	cpu_info_3			: 32; // CPU info string bytes 12 - 15
+};
+
+/*
+ * Leaf 0x80860004
+ * Transmeta CPU information string, bytes 16 - 31
+ */
+
+struct leaf_0x80860004_0 {
+	// eax
+	u32	cpu_info_4			: 32; // CPU info string bytes 16 - 19
+	// ebx
+	u32	cpu_info_5			: 32; // CPU info string bytes 20 - 23
+	// ecx
+	u32	cpu_info_6			: 32; // CPU info string bytes 24 - 27
+	// edx
+	u32	cpu_info_7			: 32; // CPU info string bytes 28 - 31
+};
+
+/*
+ * Leaf 0x80860005
+ * Transmeta CPU information string, bytes 32 - 47
+ */
+
+struct leaf_0x80860005_0 {
+	// eax
+	u32	cpu_info_8			: 32; // CPU info string bytes 32 - 35
+	// ebx
+	u32	cpu_info_9			: 32; // CPU info string bytes 36 - 39
+	// ecx
+	u32	cpu_info_10			: 32; // CPU info string bytes 40 - 43
+	// edx
+	u32	cpu_info_11			: 32; // CPU info string bytes 44 - 47
+};
+
+/*
+ * Leaf 0x80860006
+ * Transmeta CPU information string, bytes 48 - 63
+ */
+
+struct leaf_0x80860006_0 {
+	// eax
+	u32	cpu_info_12			: 32; // CPU info string bytes 48 - 51
+	// ebx
+	u32	cpu_info_13			: 32; // CPU info string bytes 52 - 55
+	// ecx
+	u32	cpu_info_14			: 32; // CPU info string bytes 56 - 59
+	// edx
+	u32	cpu_info_15			: 32; // CPU info string bytes 60 - 63
+};
+
+/*
+ * Leaf 0x80860007
+ * Transmeta live CPU information
+ */
+
+struct leaf_0x80860007_0 {
+	// eax
+	u32	cpu_cur_mhz			: 32; // Current CPU frequency, in MHz
+	// ebx
+	u32	cpu_cur_voltage			: 32; // Current CPU voltage, in millivolts
+	// ecx
+	u32	cpu_cur_perf_pctg		: 32; // Current CPU performance percentage, 0 - 100
+	// edx
+	u32	cpu_cur_gate_delay		: 32; // Current CPU gate delay, in femtoseconds
+};
+
+/*
+ * Leaf 0xc0000000
+ * Maximum Centaur/Zhaoxin leaf number
+ */
+
+struct leaf_0xc0000000_0 {
+	// eax
+	u32	max_cntr_leaf			: 32; // Maximum Centaur/Zhaoxin leaf number
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32					: 32; // Reserved
+};
+
+/*
+ * Leaf 0xc0000001
+ * Centaur/Zhaoxin extended CPU features
+ */
+
+struct leaf_0xc0000001_0 {
+	// eax
+	u32					: 32; // Reserved
+	// ebx
+	u32					: 32; // Reserved
+	// ecx
+	u32					: 32; // Reserved
+	// edx
+	u32	ccs_sm2				:  1, // CCS SM2 instructions
+		ccs_sm2_en			:  1, // CCS SM2 enabled
+		rng				:  1, // Random Number Generator
+		rng_en				:  1, // RNG enabled
+		ccs_sm3_sm4			:  1, // CCS SM3 and SM4 instructions
+		ccs_sm3_sm4_en			:  1, // CCS SM3/SM4 enabled
+		ace				:  1, // Advanced Cryptography Engine
+		ace_en				:  1, // ACE enabled
+		ace2				:  1, // Advanced Cryptography Engine v2
+		ace2_en				:  1, // ACE v2 enabled
+		phe				:  1, // PadLock Hash Engine
+		phe_en				:  1, // PHE enabled
+		pmm				:  1, // PadLock Montgomery Multiplier
+		pmm_en				:  1, // PMM enabled
+						:  2, // Reserved
+		parallax			:  1, // Parallax auto adjust processor voltage
+		parallax_en			:  1, // Parallax enabled
+						:  2, // Reserved
+		tm3				:  1, // Thermal Monitor v3
+		tm3_en				:  1, // TM v3 enabled
+						:  3, // Reserved
+		phe2				:  1, // PadLock Hash Engine v2 (SHA384/SHA512)
+		phe2_en				:  1, // PHE v2 enabled
+		rsa				:  1, // RSA instructions (XMODEXP/MONTMUL2)
+		rsa_en				:  1, // RSA instructions enabled
+						:  3; // Reserved
+};
+
+#endif /* _ASM_X86_CPUID_LEAVES */
-- 
2.49.0

[PATCH v3 20/44] x86/cpuid: Introduce a centralized CPUID data model

[Ahmed S. Darwish]

** Context

The x86-cpuid-db project generates a C header file with full C99 bitfield
listings for all known CPUID leaf/subleaf query outputs.

That header is now merged by parent commits at <asm/cpuid/leaf_types.h>,
and is in the form:

    struct leaf_0x0_0 { /* CPUID(0x0), subleaf 0, C99 bitfields */ };
    ...
    struct leaf_0x7_0 { /* CPUID(0x7), subleaf 0, C99 bitfields */ };
    struct leaf_0x7_1 { /* CPUID(0x7), subleaf 1, C99 bitfields */ };
    ...

** Goal

Introduce a structured, size-efficient, per-CPU, CPUID data repository.

Use the x86-cpuid-db auto-generated data types, and custom CPUID leaf
parsers, to build that repository.  Given a leaf, subleaf, and index,
provide direct memory access to the parsed and cached per-CPU CPUID
output.

** Long-term goal

Remove the need for drivers and other areas in the kernel to invoke
direct CPUID queries.  Only one place in the kernel should be allowed to
use the CPUID instruction: the CPUID parser code.

** Implementation

Introduce CPUID_LEAF() to build a compact CPUID storage layout in the
form:

    struct leaf_0x0_0		leaf_0x0_0[1];
    struct leaf_query_info	leaf_0x0_0_info;

    struct leaf_0x1_0		leaf_0x1_0[1];
    struct leaf_query_info	leaf_0x0_0_info;

    struct leaf_0x4_0		leaf_0x4_0[8];
    struct leaf_query_info	leaf_0x4_0_info;
     ...

where each CPUID leaf 0xN subleaf M query stores its output at the
designated leaf_0xN_M[] array and has an associated "CPUID query info"
structure.

Introduce 'struct cpuid_leaves' to group all the parsed CPUID outputs and
their metadata –in the layout above– in one structure.  Define a 'struct
cpuid_table' to wrap it, so that global per-table CPUID data can be added
later.  Embed that 'struct cpuid_table' inside 'struct cpuinfo_x86' to
ensure early-boot and per-CPU access through the current CPU's capability
structure.

Given the data layout above, and assuming a CPU capability structure 'c',
a macro can access CPUID(0x7) subleaf 0 parsed query output using the
compile time tokenization below:

    const struct leaf_0x7_0 *l7_0;

    l7_0 = cpuid_subleaf(c, 0x7, 0);
                         |   |   └────────┐
                         |   └─────────┐  |
                         *             *  *
                        &c.cpuid.leaf_0x7_0[0]

Similarly, CPUID(0x7) subleaf 1 output can be accessed using the CPP
tokenization:

    const struct leaf_0x7_1 *l7_1;

    l7_1 = cpuid_subleaf(c, 0x7, 1);
                         |   |   └────────┐
                         |   └─────────┐  |
                         *             *  *
                        &c.cpuid.leaf_0x7_1[0]

which all translate to a single assembly instruction offset calculation.

Use an array of CPUID output storage entries for each leaf/subleaf
combination to accommodate leaves which produce the same output format
for a large subleaf range.  This is typical for CPUID leaves enumerating
hierarchical objects; e.g. CPUID(0x4) cache topology enumeration,
CPUID(0xd) XSAVE enumeration, and CPUID(0x12) SGX Enclave Page Cache
enumeration.

In the CPUID_LEAF() data layout above, CPUID(0x4) has 8 storage entries
to accomodate the suleaves 0 to 7, which all have the same bitfield's
output format.  With that, CPUID(0x4) subleaves 0->7 can be accessed
using the compile time tokenization:

    const struct leaf_0x4_0 *l4_0, *l4_1, l4_2;

    l4_0 = cpuid_subleaf_index(c, 0x4, 0);
                               |   |   └──────────┐
                               |   └─────────┐    |
                               *             *    v
                              &c.cpuid.leaf_0x4_0[0]

    l4_1 = cpuid_subleaf_index(c, 0x4, 1);
                               |   |   └──────────┐
                               |   └─────────┐    |
                               *             *    v
                              &c.cpuid.leaf_0x4_0[1]

    l4_2 = cpuid_subleaf_index(c, 0x4, 2);
                               |   |   └──────────┐
                               |   └─────────┐    |
                               *             *    v
                              &c.cpuid.leaf_0x4_0[2]

where the indices 0, 1, 2 above can be provided dynamically.  This is by
design since call-sites hierarchical CPUID enumeration usually passes the
CPUID subleaf enumeration index dynamically; e.g., within a for loop.

For each of the CPUID leaf/subleaf output storage entries, attach a
'struct leaf_query_info' leaf_0xN_M_info instance.  It is to be filled by
the CPUID parsing logic filling the CPUID table(s).  For now, this info
structure has one element: the number of filled slots by the CPUID
paraser in the CPUID leaf/subleaf output storage array.

** Call-site APIs

Introduce below APIs for CPUID leaves with static subleaves:

    cpuid_subleaf(_cpuinfo, _leaf, _subleaf)
    cpuid_leaf(_cpuinfo, _leaf)
    cpuid_leaf_regs(_cpuinfo, _leaf)

And below APIs for CPUID leaves with dynamic subleaves:

    cpuid_subleaf_count(_cpuinfo, _leaf)
    cpuid_subleaf_index(_cpuinfo, _leaf, _idx)
    cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx)

At <cpuid/api.h>, add a clear rationale for why call sites should use the
above APIs instead of directly invoking CPUID queries.

** Next steps

For now, define entries for CPUID(0x0) and CPUID(0x1) in the CPUID table.
Generic CPUID parser logic to fill the per-CPU CPUID tables, along with
more CPUID leaves support, will be added next.

Suggested-by: Thomas Gleixner <tglx@linutronix.de>	# CPUID data model
Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>	# x86-cpuid-db schema
Suggested-by: Ingo Molnar <mingo@kernel.org>		# CPUID APIs restructuring
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lore.kernel.org/lkml/874ixernra.ffs@tglx
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db
---
 arch/x86/include/asm/cpuid/api.h   | 254 +++++++++++++++++++++++++++++
 arch/x86/include/asm/cpuid/types.h | 104 ++++++++++++
 arch/x86/include/asm/processor.h   |   1 +
 3 files changed, 359 insertions(+)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 2b9750cc8a75..b277c82e062f 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -289,4 +289,258 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
 	return cpuid_edx(0x80000006);
 }
 
+/*
+ * 'struct cpuid_leaves' accessors:
+ *
+ * For internal-use by the CPUID parser.  These macros do not perform any
+ * sanity checks.
+ */
+
+/**
+ * __cpuid_leaves_subleaf_idx() - Get parsed CPUID output (without sanity checks)
+ * @_leaves:	&struct cpuid_leaves instance
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format
+ * @_idx:	@_leaf/@_subleaf CPUID output's storage array index.  Check
+ *		__CPUID_LEAF() for info on CPUID output storage arrays indexing.
+ *
+ * Returns the parsed CPUID output at @_leaves as a <cpuid/leaf_types.h> data
+ * type: 'struct leaf_0xN_M', where 0xN is the token provided at @_leaf, and M
+ * is token provided at @_subleaf.
+ */
+#define __cpuid_leaves_subleaf_idx(_leaves, _leaf, _subleaf, _idx)	\
+	((_leaves)->leaf_ ## _leaf ## _ ## _subleaf)[_idx]
+
+/**
+ * __cpuid_leaves_subleaf_0() - Get parsed CPUID output (without sanity checks)
+ * @_leaves:	&struct cpuid_leaves instance
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ *
+ * Like __cpuid_leaves_subleaf_idx(), but with subleaf = 0 and index = 0.
+ */
+#define __cpuid_leaves_subleaf_0(_leaves, _leaf)			\
+	__cpuid_leaves_subleaf_idx(_leaves, _leaf, 0, 0)
+
+/**
+ * __cpuid_leaves_subleaf_info() - Get CPUID query info for @_leaf/@_subleaf
+ * @_leaves:	&struct cpuid_leaves instance
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format
+ *
+ * Returns a pointer to the &struct leaf_query_info instance associated with
+ * the given @_leaf/@_subleaf pair at the CPUID @_leaves data repository. See
+ * __CPUID_LEAF().
+ */
+#define __cpuid_leaves_subleaf_info(_leaves, _leaf, _subleaf)		\
+	((_leaves)->leaf_ ## _leaf ## _ ## _subleaf ## _ ## info)
+
+/*
+ * 'struct cpuid_table' accessors:
+ *
+ * For internal-use by the CPUID parser.  These macros perform the necessary
+ * sanity checks by default.
+ */
+
+/**
+ * __cpuid_table_subleaf_idx() - Get parsed CPUID output (with sanity checks)
+ * @_table:	&struct cpuid_table instance
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format
+ * @_idx:	@_leaf/@_subleaf CPUID query output's storage array index.
+ *		See __CPUID_LEAF().
+ *
+ * Return a pointer to the requested parsed CPUID output at @_table, as a
+ * <cpuid/leaf_types.h> data type: 'struct leaf_0xN_M', where 0xN is the token
+ * provided at @_leaf, and M is the token provided at @_subleaf; e.g. 'struct
+ * leaf_0x7_0'.
+ *
+ * Returns NULL if the requested CPUID @_leaf/@_subleaf/@_idx query output is
+ * not present at @_table.
+ */
+#define __cpuid_table_subleaf_idx(_table, _leaf, _subleaf, _idx)	\
+	(((_idx) >= __cpuid_leaves_subleaf_info(&((_table)->leaves), _leaf, _subleaf).nr_entries) ? \
+	 NULL : &__cpuid_leaves_subleaf_idx(&((_table)->leaves), _leaf, _subleaf, _idx))
+
+/**
+ * __cpuid_table_subleaf() - Get parsed CPUID output (with sanity checks)
+ * @_table:	&struct cpuid_table instance
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format
+ *
+ * Like __cpuid_table_subleaf_idx(), but with CPUID output storage index = 0.
+ */
+#define __cpuid_table_subleaf(_table, _leaf, _subleaf)			\
+	__cpuid_table_subleaf_idx(_table, _leaf, _subleaf, 0)
+
+/*
+ * External APIs for accessing parsed CPUID data:
+ *
+ * Call sites should use below APIs instead of invoking direct CPUID queries.
+ *
+ * Benefits include:
+ *
+ * - Return CPUID output as typed C structures that are auto-generated from a
+ *   centralized database (see <cpuid/leaf_types.h).  Such data types have a
+ *   full C99 bitfield layout per CPUID leaf/subleaf combination.  Call sites
+ *   can thus avoid doing ugly and cryptic bitwise operations on raw CPUID data.
+ *
+ * - Return cached, per-CPU, CPUID output.  Below APIs do not invoke any CPUID
+ *   queries, thus avoiding their side effects like serialization and VM exits.
+ *   Call-site-specific hard coded constants and macros for caching CPUID query
+ *   outputs can also be avoided.
+ *
+ * - Return sanitized CPUID data.  Below APIs return NULL if the given CPUID
+ *   leaf/subleaf input is not supported by hardware, or if the hardware CPUID
+ *   output was deemed invalid by the CPUID parser.  This centralizes all CPUID
+ *   data sanitization in one place (the kernel's CPUID parser.)
+ *
+ * - A centralized global view of system CPUID data.  Below APIs will reflect
+ *   any kernel-enforced feature masking or overrides, unlike ad hoc parsing of
+ *   raw CPUID output by drivers and individual call sites.
+ */
+
+/**
+ * cpuid_subleaf() - Access parsed CPUID data
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format; e.g. 0x7, 0xf
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format; e.g. 0, 1, 3
+ *
+ * Returns a pointer to parsed CPUID output, from the CPUID table inside
+ * @_cpuinfo, as a <cpuid/leaf_types.h> data type: 'struct leaf_0xN_M', where
+ * 0xN is the token provided at @_leaf, and M is the token provided at
+ * @_subleaf; e.g. struct leaf_0x7_0.
+ *
+ * Returns NULL if the requested CPUID @_leaf/@_subleaf query output is not
+ * present at the parsed CPUID table inside @_cpuinfo.  This can happen if:
+ *
+ * - The CPUID table inside @_cpuinfo has not yet been populated.
+ * - The CPUID table inside @_cpuinfo was populated, but the CPU does not
+ *   implement the requested CPUID @_leaf/@_subleaf combination.
+ * - The CPUID table inside @_cpuinfo was populated, but the kernel's CPUID
+ *   parser has predetermined that the requested CPUID @_leaf/@_subleaf
+ *   hardware output is invalid or unsupported.
+ *
+ * Example usage::
+ *
+ *	const struct leaf_0x7_0 *l7_0 = cpuid_subleaf(c, 0x7, 0);
+ *	if (!l7_0) {
+ *		// Handle error
+ *	}
+ *
+ *	const struct leaf_0x7_1 *l7_1 = cpuid_subleaf(c, 0x7, 1);
+ *	if (!l7_1) {
+ *		// Handle error
+ *	}
+ */
+#define cpuid_subleaf(_cpuinfo, _leaf, _subleaf)			\
+	__cpuid_table_subleaf(&_cpuinfo->cpuid, _leaf, _subleaf)
+
+/**
+ * cpuid_leaf() - Access parsed CPUID data
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format; e.g. 0x0, 0x2, 0x80000000
+ *
+ * Similar to cpuid_subleaf(), but with a CPUID subleaf = 0.
+ *
+ * Example usage::
+ *
+ *	const struct leaf_0x0_0 *l0 = cpuid_leaf(c, 0x0);
+ *	if (!l0) {
+ *		// Handle error
+ *	}
+ *
+ *	const struct leaf_0x80000000_0 *el0 = cpuid_leaf(c, 0x80000000);
+ *	if (!el0) {
+ *		// Handle error
+ *	}
+ */
+#define cpuid_leaf(_cpuinfo, _leaf)					\
+	cpuid_subleaf(_cpuinfo, _leaf, 0)
+
+/**
+ * cpuid_leaf_regs() - Access parsed CPUID data in raw format
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ *
+ * Similar to cpuid_leaf(), but returns a raw 'struct cpuid_regs' pointer to
+ * the parsed CPUID data instead of a "typed" <cpuid/leaf_types.h> pointer.
+ */
+#define cpuid_leaf_regs(_cpuinfo, _leaf)				\
+	((struct cpuid_regs *)(cpuid_leaf(_cpuinfo, _leaf)))
+
+#define __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf)	\
+	static_assert(ARRAY_SIZE(_cpuinfo->cpuid.leaves.leaf_ ## _leaf ## _0) > 1);
+
+/**
+ * cpuid_subleaf_index() - Access parsed CPUID data at runtime subleaf index
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d
+ * @_idx:	Index within CPUID(@_leaf) output storage array.  It must be
+ *		smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)".  Unlike
+ *		@_leaf, this value can be provided dynamically.
+ *
+ * For a given leaf/subleaf combination, the CPUID table inside @_cpuinfo
+ * contains an array of CPUID output storage entries.  An array of storage
+ * entries is used to accommodate CPUID leaves which produce the same output
+ * format for a large subleaf range.  This is common for CPUID hierarchical
+ * objects enumeration; e.g., CPUID(0x4) and CPUID(0xd).  Check CPUID_LEAF().
+ *
+ * CPUID leaves that are to be accessed using this macro are specified at
+ * <cpuid/types.h>, 'struct cpuid_leaves', with a CPUID_LEAF() count field
+ * bigger than 1.  A build-time error will be generated otherwise.
+ *
+ * Example usage::
+ *
+ *	const struct leaf_0x4_0 *l4;
+ *
+ *	for (int i = 0; i < cpuid_subleaf_count(c, 0x4); i++) {
+ *		l4 = cpuid_subleaf_index(c, 0x4, i);
+ *		if (!l4) {
+ *			// Handle error
+ *		}
+ *
+ *		// Access CPUID(0x4, i) data; e.g. l4->cache_type
+ *	}
+ *
+ * Beside the standard error situations detailed at cpuid_subleaf(), this
+ * macro will return NULL if @_idx is out of range.
+ */
+#define cpuid_subleaf_index(_cpuinfo, _leaf, _idx)			\
+({									\
+	__cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf);	\
+	__cpuid_table_subleaf_idx(&_cpuinfo->cpuid, _leaf, 0, _idx);	\
+})
+
+/**
+ * cpuid_subleaf_index_regs() - Access parsed CPUID data at runtime subleaf index
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d
+ * @_idx:	Index within CPUID(@_leaf) output storage array.  It must be
+ *		smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)".
+ *
+ * Similar to cpuid_subleaf_index(), but returns a raw 'struct cpuid_regs'
+ * pointer to the parsed CPUID data, instead of a "typed" <cpuid/leaf_types.h>
+ * pointer.
+ */
+#define cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx)			\
+	((struct cpuid_regs *)cpuid_subleaf_index(_cpuinfo, _leaf, _idx))
+
+/**
+ * cpuid_subleaf_count() - Number of valid (filled) subleaves for @_leaf
+ * @_cpuinfo:	CPU capability structure reference ('struct cpuinfo_x86')
+ * @_leaf:	CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d
+ *
+ * Return the number of subleaves filled by the CPUID parser for @_leaf. Check
+ * cpuid_subleaf_index().
+ *
+ * CPUID leaves that are to be accessed using this macro are specified at
+ * <cpuid/types.h>, 'struct cpuid_leaves', with a CPUID_LEAF() count field
+ * bigger than 1.  A build-time error will be generated otherwise.
+ */
+#define cpuid_subleaf_count(_cpuinfo, _leaf)				\
+({									\
+	__cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf);	\
+	__cpuid_leaves_subleaf_info(&_cpuinfo->cpuid.leaves, _leaf, 0).nr_entries;\
+})
+
 #endif /* _ASM_X86_CPUID_API_H */
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 8a00364b79de..f1b51ba21ca4 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -5,6 +5,8 @@
 #include <linux/build_bug.h>
 #include <linux/types.h>
 
+#include <asm/cpuid/leaf_types.h>
+
 /*
  * Types for raw CPUID access:
  */
@@ -124,4 +126,106 @@ extern const struct leaf_0x2_table cpuid_0x2_table[256];
  */
 #define TLB_0x63_2M_4M_ENTRIES		32
 
+/*
+ * Types for centralized CPUID tables:
+ *
+ * For internal use by the CPUID parser.
+ */
+
+/**
+ * struct leaf_query_info - Parse info for a CPUID leaf/subleaf query
+ * @nr_entries:	Number of valid output storage entries filled by the CPUID parser
+ *
+ * In a CPUID table (struct cpuid_leaves), each CPUID leaf/subleaf query output
+ * storage entry from <cpuid/leaf_types.h> is paired with a unique instance of
+ * this type.
+ */
+struct leaf_query_info {
+	unsigned int		nr_entries;
+};
+
+/**
+ * __CPUID_LEAF() - Define CPUID output storage and query info entry
+ * @_name:	Struct type name of the CPUID leaf/subleaf (e.g. 'leaf_0x4_0').
+ *		Such types are defined at <cpuid/leaf_types.h>, and follow the
+ *		format 'struct leaf_0xN_M', where 0xN is the leaf and M is the
+ *		subleaf.
+ * @_count:	Number of storage entries to allocate for this leaf/subleaf
+ *
+ * For the given leaf/subleaf combination, define an array of CPUID output
+ * storage entries and an associated query info structure — both residing in a
+ * 'struct cpuid_leaves' instance.
+ *
+ * Use an array of storage entries to accommodate CPUID leaves which produce
+ * the same output format for a large subleaf range.  This is common for
+ * hierarchical objects enumeration; e.g., CPUID(0x4), CPUID(0xd), and
+ * CPUID(0x12).
+ *
+ * The example invocation for CPUID(0x7) storage, subleaves 0->1:
+ *
+ *	__CPUID_LEAF(leaf_0x7_0, 1);
+ *	__CPUID_LEAF(leaf_0x7_1, 1);
+ *
+ * generates 'struct cpuid_leaves' storage entries in the form::
+ *
+ *	struct leaf_0x7_0		leaf_0x7_0[1];
+ *	struct leaf_query_info		leaf_0x7_0_info;
+ *
+ *	struct leaf_0x7_1		leaf_0x7_1[1];
+ *	struct leaf_query_info		leaf_0x7_1_info;
+ *
+ * The example invocation for CPUID(0x4) storage::
+ *
+ *	__CPUID_LEAF(leaf_0x4_0, 8);
+ *
+ * generates storage entries in the form:
+ *
+ *	struct leaf_0x4_0		leaf_0x4_0[8];
+ *	struct leaf_query_info		leaf_0x4_0_info;
+ *
+ * where the 'leaf_0x4_0[8]' storage array can accommodate the output of
+ * CPUID(0x4) subleaves 0->7, since they all have the same output format.
+ */
+#define __CPUID_LEAF(_name, _count)				\
+	struct _name		_name[_count];			\
+	struct leaf_query_info	_name##_info
+
+/**
+ * CPUID_LEAF() - Define a CPUID storage entry in 'struct cpuid_leaves'
+ * @_leaf:	CPUID Leaf number in the 0xN format; e.g., 0x4.
+ * @_subleaf:	Subleaf number in decimal
+ * @_count:	Number of repeated storage entries for this @_leaf/@_subleaf
+ *
+ * Convenience wrapper around __CPUID_LEAF().
+ */
+#define CPUID_LEAF(_leaf, _subleaf, _count)			\
+	__CPUID_LEAF(leaf_ ## _leaf ## _ ## _subleaf, _count)
+
+/*
+ * struct cpuid_leaves - Structured CPUID data repository
+ */
+struct cpuid_leaves {
+	/*         leaf		subleaf		count */
+	CPUID_LEAF(0x0,		0,		1);
+	CPUID_LEAF(0x1,		0,		1);
+};
+
+/*
+ * Types for centralized CPUID tables:
+ *
+ * For external use.
+ */
+
+/**
+ * struct cpuid_table - Per-CPU CPUID data repository
+ * @leaves:	CPUID leaf/subleaf queries' output and metadata
+ *
+ * Embedded inside 'struct cpuinfo_x86' to provide access to stored, parsed,
+ * and sanitized CPUID output per-CPU.  Thus removing the need for any direct
+ * CPUID query by call sites.
+ */
+struct cpuid_table {
+	struct cpuid_leaves	leaves;
+};
+
 #endif /* _ASM_X86_CPUID_TYPES_H */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index bde58f6510ac..b5d90b60191b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -165,6 +165,7 @@ struct cpuinfo_x86 {
 	char			x86_vendor_id[16];
 	char			x86_model_id[64];
 	struct cpuinfo_topology	topo;
+	struct cpuid_table	cpuid;
 	/* in KB - valid for CPUS which support this call: */
 	unsigned int		x86_cache_size;
 	int			x86_cache_alignment;	/* In bytes */
-- 
2.49.0

[PATCH v3 21/44] x86/cpuid: Introduce a centralized CPUID parser

[Ahmed S. Darwish]

Introduce a centralized CPUID parser to populate the per-CPU CPUID
tables.  To ensures consistent and early availablity of parsed CPUID
data, invoke this parser during both early boot and secondary CPUs bring
up.

Since accessing the CPUID leaf output storage areas at 'struct
cpuid_table' requires compile time tokenization, split the parser
implementation into two stages: compile time macros for tokenizing the
leaf/subleaf output offsets within a CPUID table, and generic runtime
code to access and populate the relevant CPUID leaf/subleaf data
structures using such offsets.

For flexible parsing of CPUID leaf/subleaf outputs, support both generic
and leaf-specific CPUID read functions.

Note, add three section headers to cpuid_parser.c: "Leaf read functions",
"Leaf-independent parser code", and "Exported APIs".  Each section will
be further expanded next.

Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h   |   7 ++
 arch/x86/include/asm/cpuid/types.h |   3 +
 arch/x86/kernel/cpu/Makefile       |   1 +
 arch/x86/kernel/cpu/common.c       |   2 +
 arch/x86/kernel/cpu/cpuid_parser.c | 114 +++++++++++++++++++++++++++++
 arch/x86/kernel/cpu/cpuid_parser.h | 100 +++++++++++++++++++++++++
 6 files changed, 227 insertions(+)
 create mode 100644 arch/x86/kernel/cpu/cpuid_parser.c
 create mode 100644 arch/x86/kernel/cpu/cpuid_parser.h

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index b277c82e062f..dbc954e21b7e 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -7,6 +7,7 @@
 #include <linux/build_bug.h>
 #include <linux/types.h>
 
+#include <asm/processor.h>
 #include <asm/string.h>
 
 /*
@@ -543,4 +544,10 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
 	__cpuid_leaves_subleaf_info(&_cpuinfo->cpuid.leaves, _leaf, 0).nr_entries;\
 })
 
+/*
+ * CPUID parser exported APIs:
+ */
+
+void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c);
+
 #endif /* _ASM_X86_CPUID_API_H */
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index f1b51ba21ca4..320f152675af 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -32,6 +32,9 @@ enum cpuid_regs_idx {
 #define CPUID_LEAF_FREQ		0x16
 #define CPUID_LEAF_TILE		0x1d
 
+#define CPUID_BASE_START	0x0
+#define CPUID_BASE_END		(CPUID_BASE_START + 0xffff)
+
 /*
  * Types for CPUID(0x2) parsing:
  */
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 1e26179ff18c..b2421cfb59ed 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -19,6 +19,7 @@ KCSAN_SANITIZE_common.o := n
 
 obj-y			:= cacheinfo.o scattered.o
 obj-y			+= topology_common.o topology_ext.o topology_amd.o
+obj-y			+= cpuid_parser.o
 obj-y			+= common.o
 obj-y			+= rdrand.o
 obj-y			+= match.o
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8feb8fd2957a..8aa3ba269c0b 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1716,6 +1716,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 
 	/* cyrix could have cpuid enabled via c_identify()*/
 	if (cpuid_feature()) {
+		cpuid_parser_scan_cpu(c);
 		cpu_detect(c);
 		get_cpu_vendor(c);
 		intel_unlock_cpuid_leafs(c);
@@ -2096,6 +2097,7 @@ void identify_secondary_cpu(unsigned int cpu)
 		*c = boot_cpu_data;
 	c->cpu_index = cpu;
 
+	cpuid_parser_scan_cpu(c);
 	identify_cpu(c);
 #ifdef CONFIG_X86_32
 	enable_sep_cpu();
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
new file mode 100644
index 000000000000..3a0215e75795
--- /dev/null
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Centralized CPUID parser (for populating the system's CPUID tables.)
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/cpuid/api.h>
+#include <asm/percpu.h>
+#include <asm/processor.h>
+
+#include "cpuid_parser.h"
+
+/*
+ * Leaf read functions:
+ */
+
+/*
+ * Default CPUID parser read function
+ *
+ * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read().
+ */
+static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
+{
+	for (int i = 0; i < e->maxcnt; i++, output->regs++, output->info->nr_entries++)
+		cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs);
+}
+
+/*
+ * Leaf-independent parser code:
+ */
+
+static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsigned int range)
+{
+	switch (range) {
+	case CPUID_BASE_START:	return __cpuid_leaves_subleaf_0(&t->leaves, 0x0).max_std_leaf;
+	default:		return 0;
+	}
+}
+
+static bool
+cpuid_range_valid(const struct cpuid_table *t, unsigned int leaf, unsigned int start, unsigned int end)
+{
+	if (leaf < start || leaf > end)
+		return false;
+
+	return leaf == start || leaf <= cpuid_range_max_leaf(t, start);
+}
+
+static bool cpuid_leaf_valid(const struct cpuid_table *t, unsigned int leaf)
+{
+	return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END);
+}
+
+static const struct cpuid_parse_entry cpuid_common_parse_entries[] = {
+	CPUID_PARSE_ENTRIES
+};
+
+static void
+cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry entries[], unsigned int nr_entries)
+{
+	const struct cpuid_parse_entry *entry = entries;
+
+	for (unsigned int i = 0; i < nr_entries; i++, entry++) {
+		struct cpuid_read_output output = {
+			.regs	= cpuid_table_query_regs_p(t, entry->regs_offs),
+			.info	= cpuid_table_query_info_p(t, entry->info_offs),
+		};
+
+		if (!cpuid_leaf_valid(t, entry->leaf))
+			continue;
+
+		WARN_ON_ONCE(output.info->nr_entries != 0);
+		entry->read(entry, &output);
+	}
+}
+
+/*
+ * Exported APIs:
+ */
+
+/**
+ * cpuid_parser_scan_cpu() - Populate current CPU's CPUID table
+ * @c:		CPU capability structure associated with the current CPU
+ *
+ * Populate the CPUID table embedded within @c with parsed CPUID data.  Since all CPUID
+ * instructions are invoked locally, this must be called on the CPU associated with @c.
+ */
+void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c)
+{
+	struct cpuid_table *table = &c->cpuid;
+
+	/*
+	 * For correctness, clear the CPUID table first.
+	 *
+	 * This is due to the CPUID leaf access APIs at <cpuid/api.h> using the leaf's
+	 * "nr_entries" field as a validity check.  If the field is non-zero, the macros
+	 * assume that the cached leaf outputs are valid and return them.  Otherwise, NULL
+	 * is returned.
+	 *
+	 * On the primary CPU, the CPUID tables are zeroed at boot.  For secondary CPUs,
+	 * the capability structures (containing the CPUID table) are copied from the
+	 * primary CPU.  This would result in a "nr_entries" values carry-over from the
+	 * primary CPU unless the table is explicitly cleared.
+	 *
+	 * Also, for CPUID table re-scans, which are triggered by hardware state changes,
+	 * previously valid CPUID leaves might become invalid.  The CPUID table, and its
+	 * leaves' "nr_entries" fields, must thus be cleared beforehand.
+	 */
+	memset(table, 0, sizeof(*table));
+
+	cpuid_fill_table(table, cpuid_common_parse_entries, ARRAY_SIZE(cpuid_common_parse_entries));
+}
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
new file mode 100644
index 000000000000..41499fa36fdc
--- /dev/null
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ARCH_X86_CPUID_PARSER_H
+#define _ARCH_X86_CPUID_PARSER_H
+
+#include <asm/cpuid/types.h>
+
+/*
+ * 'struct cpuid_leaves' CPUID query output storage area accessors:
+ *
+ * @_leaf:	CPUID leaf, in compile-time 0xN format
+ * @_subleaf:	CPUID subleaf, in compile-time decimal format
+ *
+ * Since accessing the CPUID leaf output storage areas at 'struct cpuid_leaves' requires
+ * compile time tokenization, split the CPUID parser implementation into two stages:
+ * compile time macros for tokenizing the leaf/subleaf output offsets within the CPUID
+ * table, and generic runtime code to access and populate the relevant CPUID leaf/subleaf
+ * output data structures using such offsets.
+ *
+ * That is, the output of the  __cpuid_leaves_query_*_offset() macros will be cached by a
+ * compile time "parse entry" (see 'struct cpuid_parse_entry').  The runtime parser code
+ * will then utilize such offsets by passing them to cpuid_table_query_*_p() functions.
+ */
+
+#define __cpuid_leaves_query_regs_offset(_leaf, _subleaf)			\
+	offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf)
+
+#define __cpuid_leaves_query_info_offset(_leaf, _subleaf)			\
+	offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf ## _ ## info)
+
+#define __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf)			\
+	ARRAY_SIZE(((struct cpuid_leaves *)NULL)->leaf_ ## _leaf ## _ ## _subleaf)
+
+static inline struct cpuid_regs *
+cpuid_table_query_regs_p(const struct cpuid_table *t, unsigned long regs_offset)
+{
+	return (struct cpuid_regs *)((unsigned long)(&t->leaves) + regs_offset);
+}
+
+static inline struct leaf_query_info *
+cpuid_table_query_info_p(const struct cpuid_table *t, unsigned long info_offset)
+{
+	return (struct leaf_query_info *)((unsigned long)(&t->leaves) + info_offset);
+}
+
+/**
+ * struct cpuid_read_output - Output of a CPUID parser read operation
+ * @regs:	Pointer to an array of CPUID outputs, where each array element covers the
+ *		full EAX->EDX output range.
+ * @info:	Pointer to query info; for saving the number of filled @regs array elements.
+ *
+ * A CPUID parser read function like cpuid_read_generic() or cpuid_read_0xN() uses this
+ * structure to save its CPUID query outputs.  Actual storage for @regs and @info is provided
+ * by its caller, and is typically within a CPU's CPUID table (struct cpuid_table.leaves).
+ *
+ * See struct cpuid_parse_entry.read().
+ */
+struct cpuid_read_output {
+	struct cpuid_regs	*regs;
+	struct leaf_query_info	*info;
+};
+
+/**
+ * struct cpuid_parse_entry - Runtime CPUID parsing context for @leaf/@subleaf
+ * @leaf:	Leaf number to be parsed
+ * @subleaf:	Subleaf number to be parsed
+ * @regs_offs:	Offset within 'struct cpuid_leaves' for saving CPUID @leaf/@subleaf output; to be
+ *		passed to cpuid_table_query_regs_p().
+ * @info_offs:	Offset within 'struct cpuid_leaves' for accessing @leaf/@subleaf parse info; to be
+ *		passed to cpuid_table_query_info_p().
+ * @maxcnt:	Maximum number of output storage entries available for the @leaf/@subleaf query
+ * @read:	Read function for this entry.  It must save the parsed CPUID output to the passed
+ *		'struct cpuid_read_output'->regs registers array of size >= @maxcnt.  It must set
+ *		'struct cpuid_read_output'->info.nr_entries to the actual number of storage output
+ *		entries filled.  A generic implementation is provided at cpuid_read_generic().
+ */
+struct cpuid_parse_entry {
+	unsigned int	leaf;
+	unsigned int	subleaf;
+	unsigned int	regs_offs;
+	unsigned int	info_offs;
+	unsigned int	maxcnt;
+	void		(*read)(const struct cpuid_parse_entry *e, struct cpuid_read_output *o);
+};
+
+#define CPUID_PARSE_ENTRY(_leaf, _subleaf, _reader_fn)					\
+	{										\
+		.leaf		= _leaf,						\
+		.subleaf	= _subleaf,						\
+		.regs_offs	= __cpuid_leaves_query_regs_offset(_leaf, _subleaf),	\
+		.info_offs	= __cpuid_leaves_query_info_offset(_leaf, _subleaf),	\
+		.maxcnt		= __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf),	\
+		.read		= cpuid_read_ ## _reader_fn,				\
+	}
+
+#define CPUID_PARSE_ENTRIES								\
+	/*		  Leaf		Subleaf		Reader function */		\
+	CPUID_PARSE_ENTRY(0x0,		0,		generic),			\
+	CPUID_PARSE_ENTRY(0x1,		0,		generic),			\
+
+#endif /* _ARCH_X86_CPUID_PARSER_H */
-- 
2.49.0

[PATCH v3 22/44] x86/cpuid: Parse CPUID(0x80000000)

[Ahmed S. Darwish]

Add CPUID parser logic for CPUID(0x80000000).

Similar to kernel/head_32.S and kernel/cpu/common.c, verify the
CPUID(0x80000000) query output beforehand.  This is due to x86-32
machines without an extended CPUID range, where a CPUID(0x80000000) query
will just repeat the max-valid standard CPUID leaf output.

References: 8a50e5135af0 ("x86-32: Use symbolic constants, safer CPUID when enabling EFER.NX")
References: 67ad24e6d39c ("- pre5:    - Rasmus Andersen: add proper...")  # Historical git
Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Link: https://lore.kernel.org/r/d4fcfd91-cc92-4b3c-9dd2-56ecd754cecc@citrix.com
---
 arch/x86/include/asm/cpuid/types.h |  7 ++++++-
 arch/x86/kernel/cpu/cpuid_parser.c | 27 ++++++++++++++++++++++++++-
 arch/x86/kernel/cpu/cpuid_parser.h |  1 +
 3 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 320f152675af..d0f0e6a8a457 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -33,7 +33,11 @@ enum cpuid_regs_idx {
 #define CPUID_LEAF_TILE		0x1d
 
 #define CPUID_BASE_START	0x0
-#define CPUID_BASE_END		(CPUID_BASE_START + 0xffff)
+#define CPUID_EXT_START		0x80000000
+
+#define __CPUID_RANGE_END(idx)	((idx) + 0xffff)
+#define CPUID_BASE_END		__CPUID_RANGE_END(CPUID_BASE_START)
+#define CPUID_EXT_END		__CPUID_RANGE_END(CPUID_EXT_START)
 
 /*
  * Types for CPUID(0x2) parsing:
@@ -211,6 +215,7 @@ struct cpuid_leaves {
 	/*         leaf		subleaf		count */
 	CPUID_LEAF(0x0,		0,		1);
 	CPUID_LEAF(0x1,		0,		1);
+	CPUID_LEAF(0x80000000,	0,		1);
 };
 
 /*
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
index 3a0215e75795..e4c45658c75f 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.c
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -31,10 +31,34 @@ static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct cpuid_r
  * Leaf-independent parser code:
  */
 
+static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
+{
+	struct leaf_0x80000000_0 *l = (struct leaf_0x80000000_0 *)output->regs;
+
+	cpuid_read_subleaf(e->leaf, e->subleaf, l);
+
+	/*
+	 * Protect against 32-bit CPUs lacking an extended CPUID range: Ensure that the
+	 * returned max extended CPUID leaf is in the 0x80000001-0x8000ffff range.
+	 *
+	 * Do not depend on leaving 'info->nr_entries' set as zero, but zero-out the
+	 * whole leaf output area as well.  This is due to the CPUID parser internals
+	 * using the __cpuid_leaves_subleaf_0() API to get the cached max extended leaf,
+	 * which does not do any sanity checks,
+	 */
+	if ((l->max_ext_leaf & 0xffff0000) != 0x80000000) {
+		*l = (struct leaf_0x80000000_0){ };
+		return;
+	}
+
+	output->info->nr_entries = 1;
+}
+
 static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsigned int range)
 {
 	switch (range) {
 	case CPUID_BASE_START:	return __cpuid_leaves_subleaf_0(&t->leaves, 0x0).max_std_leaf;
+	case CPUID_EXT_START:   return __cpuid_leaves_subleaf_0(&t->leaves, 0x80000000).max_ext_leaf;
 	default:		return 0;
 	}
 }
@@ -50,7 +74,8 @@ cpuid_range_valid(const struct cpuid_table *t, unsigned int leaf, unsigned int s
 
 static bool cpuid_leaf_valid(const struct cpuid_table *t, unsigned int leaf)
 {
-	return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END);
+	return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END) ||
+	       cpuid_range_valid(t, leaf, CPUID_EXT_START, CPUID_EXT_END);
 }
 
 static const struct cpuid_parse_entry cpuid_common_parse_entries[] = {
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index 41499fa36fdc..49b7e739852d 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -96,5 +96,6 @@ struct cpuid_parse_entry {
 	/*		  Leaf		Subleaf		Reader function */		\
 	CPUID_PARSE_ENTRY(0x0,		0,		generic),			\
 	CPUID_PARSE_ENTRY(0x1,		0,		generic),			\
+	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),
 
 #endif /* _ARCH_X86_CPUID_PARSER_H */
-- 
2.49.0

[PATCH v3 23/44] x86/cpuid: Introduce CPUID parser debugfs interface

[Ahmed S. Darwish]

Introduce the debugfs files 'x86/cpuid/[0-ncpus]' to dump each CPU's
cached CPUID table.  For each cached CPUID leaf/subleaf, invoke the
CPUID instruction on the target CPU and compare the hardware result
against the cached values.

Mark any mismatched cached CPUID output value with an asterisk.  This
should help with tricky bug reports in the future, if/when the cached
CPUID tables get unexpectedly out of sync with actual hardware state.  It
also simplifies the development and testing of adding new CPUID leaves to
the CPUID parser.

Note, expose cpuid_common_parse_entries[] via "cpuid_parser.h" to allow
the debugfs code to traverse and dump the parsed CPUID data.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/Makefile        |   2 +-
 arch/x86/kernel/cpu/cpuid_debugfs.c | 102 ++++++++++++++++++++++++++++
 arch/x86/kernel/cpu/cpuid_parser.c  |   6 +-
 arch/x86/kernel/cpu/cpuid_parser.h  |   3 +
 4 files changed, 110 insertions(+), 3 deletions(-)
 create mode 100644 arch/x86/kernel/cpu/cpuid_debugfs.c

diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index b2421cfb59ed..4e032ad851c7 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -61,7 +61,7 @@ obj-$(CONFIG_X86_LOCAL_APIC)		+= perfctr-watchdog.o
 obj-$(CONFIG_HYPERVISOR_GUEST)		+= vmware.o hypervisor.o mshyperv.o
 obj-$(CONFIG_ACRN_GUEST)		+= acrn.o
 
-obj-$(CONFIG_DEBUG_FS)			+= debugfs.o
+obj-$(CONFIG_DEBUG_FS)			+= debugfs.o cpuid_debugfs.o
 
 obj-$(CONFIG_X86_BUS_LOCK_DETECT)	+= bus_lock.o
 
diff --git a/arch/x86/kernel/cpu/cpuid_debugfs.c b/arch/x86/kernel/cpu/cpuid_debugfs.c
new file mode 100644
index 000000000000..99ebbd14b139
--- /dev/null
+++ b/arch/x86/kernel/cpu/cpuid_debugfs.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * CPUID parser debugfs entries: x86/cpuid/[0-ncpus]
+ *
+ * Dump each CPU's cached CPUID table and compare its values against current
+ * CPUID output on that CPU.  Mark changed entries with an asterisk.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/types.h>
+
+#include <asm/cpuid/api.h>
+#include <asm/percpu.h>
+#include <asm/processor.h>
+
+#include "cpuid_parser.h"
+
+static void cpuid_this_cpu(void *info)
+{
+	struct cpuid_regs *regs = info;
+
+	__cpuid(&regs->eax, &regs->ebx, &regs->ecx, &regs->edx);
+}
+
+static void
+cpuid_show_leaf(struct seq_file *m, uintptr_t cpu_id, const struct cpuid_parse_entry *entry,
+		const struct leaf_query_info *info, const struct cpuid_regs *cached)
+{
+	for (int j = 0; j < info->nr_entries; j++) {
+		u32 subleaf = entry->subleaf + j;
+		struct cpuid_regs regs = {
+			.eax = entry->leaf,
+			.ecx = subleaf,
+		};
+		int ret;
+
+		seq_printf(m, "Leaf 0x%08x, subleaf %u:\n", entry->leaf, subleaf);
+
+		ret = smp_call_function_single(cpu_id, cpuid_this_cpu, &regs, true);
+		if (ret) {
+			seq_printf(m, "Failed to invoke CPUID on CPU %lu: %d\n\n", cpu_id, ret);
+			continue;
+		}
+
+		seq_printf(m, "  cached:   %cEAX=0x%08x   %cEBX=0x%08x   %cECX=0x%08x   %cEDX=0x%08x\n",
+			   cached[j].eax == regs.eax ? ' ' : '*', cached[j].eax,
+			   cached[j].ebx == regs.ebx ? ' ' : '*', cached[j].ebx,
+			   cached[j].ecx == regs.ecx ? ' ' : '*', cached[j].ecx,
+			   cached[j].edx == regs.edx ? ' ' : '*', cached[j].edx);
+		seq_printf(m, "  actual:    EAX=0x%08x    EBX=0x%08x    ECX=0x%08x    EDX=0x%08x\n",
+			   regs.eax, regs.ebx, regs.ecx, regs.edx);
+	}
+}
+
+static int cpuid_debug_show(struct seq_file *m, void *p)
+{
+	uintptr_t cpu_id = (uintptr_t)m->private;
+	const struct cpuinfo_x86 *c = per_cpu_ptr(&cpu_info, cpu_id);
+	const struct cpuid_table *t = &c->cpuid;
+
+	const struct cpuid_parse_entry *entry = cpuid_common_parse_entries;
+
+	for (unsigned int i = 0; i < cpuid_common_parse_entries_size; i++, entry++) {
+		const struct leaf_query_info *qi = cpuid_table_query_info_p(t, entry->info_offs);
+		const struct cpuid_regs *qr = cpuid_table_query_regs_p(t, entry->regs_offs);
+
+		cpuid_show_leaf(m, cpu_id, entry, qi, qr);
+	}
+
+	return 0;
+}
+
+static int cpuid_debug_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, cpuid_debug_show, inode->i_private);
+}
+
+static const struct file_operations cpuid_ops = {
+	.open		= cpuid_debug_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static __init int cpuid_init_debugfs(void)
+{
+	struct dentry *dir;
+	uintptr_t cpu_id;
+	char cpu_name[24];
+
+	dir = debugfs_create_dir("cpuid", arch_debugfs_dir);
+
+	for_each_possible_cpu(cpu_id) {
+		scnprintf(cpu_name, sizeof(cpu_name), "%lu", cpu_id);
+		debugfs_create_file(cpu_name, 0444, dir, (void *)cpu_id, &cpuid_ops);
+	}
+
+	return 0;
+}
+late_initcall(cpuid_init_debugfs);
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
index e4c45658c75f..eb8975de497a 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.c
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -78,10 +78,12 @@ static bool cpuid_leaf_valid(const struct cpuid_table *t, unsigned int leaf)
 	       cpuid_range_valid(t, leaf, CPUID_EXT_START, CPUID_EXT_END);
 }
 
-static const struct cpuid_parse_entry cpuid_common_parse_entries[] = {
+const struct cpuid_parse_entry cpuid_common_parse_entries[] = {
 	CPUID_PARSE_ENTRIES
 };
 
+const int cpuid_common_parse_entries_size = ARRAY_SIZE(cpuid_common_parse_entries);
+
 static void
 cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry entries[], unsigned int nr_entries)
 {
@@ -135,5 +137,5 @@ void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c)
 	 */
 	memset(table, 0, sizeof(*table));
 
-	cpuid_fill_table(table, cpuid_common_parse_entries, ARRAY_SIZE(cpuid_common_parse_entries));
+	cpuid_fill_table(table, cpuid_common_parse_entries, cpuid_common_parse_entries_size);
 }
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index 49b7e739852d..882e96b000ba 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -98,4 +98,7 @@ struct cpuid_parse_entry {
 	CPUID_PARSE_ENTRY(0x1,		0,		generic),			\
 	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),
 
+extern const struct cpuid_parse_entry cpuid_common_parse_entries[];
+extern const int cpuid_common_parse_entries_size;
+
 #endif /* _ARCH_X86_CPUID_PARSER_H */
-- 
2.49.0

[PATCH v3 24/44] x86/cpu: Use parsed CPUID(0x0)

[Ahmed S. Darwish]

Use parsed CPUID(0x0) access instead of a direct CPUID query.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/common.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8aa3ba269c0b..234d0f5de39e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -895,11 +895,12 @@ void get_cpu_vendor(struct cpuinfo_x86 *c)
 
 void cpu_detect(struct cpuinfo_x86 *c)
 {
-	/* Get vendor name */
-	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
-	      (unsigned int *)&c->x86_vendor_id[0],
-	      (unsigned int *)&c->x86_vendor_id[8],
-	      (unsigned int *)&c->x86_vendor_id[4]);
+	const struct leaf_0x0_0 *l0 = cpuid_leaf(c, 0x0);
+
+	c->cpuid_level = l0->max_std_leaf;
+	*(u32 *)&c->x86_vendor_id[0] = l0->cpu_vendorid_0;
+	*(u32 *)&c->x86_vendor_id[4] = l0->cpu_vendorid_1;
+	*(u32 *)&c->x86_vendor_id[8] = l0->cpu_vendorid_2;
 
 	c->x86 = 4;
 	/* Intel-defined flags: level 0x00000001 */
-- 
2.49.0

[PATCH v3 25/44] x86/cpu: Use parsed CPUID(0x80000000)

[Ahmed S. Darwish]

Use parsed CPUID(0x80000000) access instead of a direct CPUID query.

The affected code has the check:

	(eax & 0xffff0000) == 0x80000000

to protect against Intel 32-bit CPUs that lack extended CPUID support.  A
similar check is already done at the CPUID(0x80000000) scanner read
function at cpuid_parser.c:

	/*
	 * Protect against 32-bit CPUs lacking extended CPUID support: Max
	 * extended CPUID leaf must be in the 0x80000001-0x8000ffff range.
	 */
	if ((l->max_ext_leaf & 0xffff0000) != 0x80000000) {
		// Handle error
	}

Thus, just check that the parsed CPUID macro:

	cpuid_leaf(c, 0x80000000)

does not return NULL, thus providing a sanity check similar to the
original code.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/common.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 234d0f5de39e..b3408ae2b144 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -972,6 +972,7 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
 
 void get_cpu_cap(struct cpuinfo_x86 *c)
 {
+	const struct leaf_0x80000000_0 *el0;
 	u32 eax, ebx, ecx, edx;
 
 	/* Intel-defined flags: level 0x00000001 */
@@ -1007,12 +1008,8 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
 		c->x86_capability[CPUID_D_1_EAX] = eax;
 	}
 
-	/*
-	 * Check if extended CPUID leaves are implemented: Max extended
-	 * CPUID leaf must be in the 0x80000001-0x8000ffff range.
-	 */
-	eax = cpuid_eax(0x80000000);
-	c->extended_cpuid_level = ((eax & 0xffff0000) == 0x80000000) ? eax : 0;
+	el0 = cpuid_leaf(c, 0x80000000);
+	c->extended_cpuid_level = (el0) ? el0->max_ext_leaf : 0;
 
 	if (c->extended_cpuid_level >= 0x80000001) {
 		cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
-- 
2.49.0

[PATCH v3 26/44] x86/lib: Add CPUID(0x1) CPU family and model calculation

[Ahmed S. Darwish]

The x86 library code provides x86_family() and x86_model().  They take
raw CPUID(0x1) EAX register output, extract the necessary bitfields with
bitwise operations, then calculate out the CPU family and model.

In follow-up commits, the x86 code will use parsed CPUID access, along
with its auto-generated <cpuid/leaf_types.h> CPUID leaf data structures
and their detailed C99 bitfields.

Introduce CPU family and model calculation functions to x86/lib that take
the auto-generated 'struct leaf_0x1_0' data type.  Refactor the pure CPU
family and model calculation logic into internal static functions so that
no logic is duplicated.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpu.h |  6 ++++++
 arch/x86/lib/cpu.c         | 41 ++++++++++++++++++++++----------------
 2 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index ad235dda1ded..90902cd91335 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -7,7 +7,9 @@
 #include <linux/topology.h>
 #include <linux/nodemask.h>
 #include <linux/percpu.h>
+
 #include <asm/ibt.h>
+#include <asm/cpuid/leaf_types.h>
 
 #ifndef CONFIG_SMP
 #define cpu_physical_id(cpu)			boot_cpu_physical_apicid
@@ -25,6 +27,10 @@ int mwait_usable(const struct cpuinfo_x86 *);
 unsigned int x86_family(unsigned int sig);
 unsigned int x86_model(unsigned int sig);
 unsigned int x86_stepping(unsigned int sig);
+
+unsigned int cpuid_family(const struct leaf_0x1_0 *l);
+unsigned int cpuid_model(const struct leaf_0x1_0 *l);
+
 #ifdef CONFIG_X86_BUS_LOCK_DETECT
 extern void __init sld_setup(struct cpuinfo_x86 *c);
 extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
index 7ad68917a51e..eac217d637ac 100644
--- a/arch/x86/lib/cpu.c
+++ b/arch/x86/lib/cpu.c
@@ -1,36 +1,43 @@
 // SPDX-License-Identifier: GPL-2.0-only
 #include <linux/types.h>
 #include <linux/export.h>
+
 #include <asm/cpu.h>
+#include <asm/cpuid/leaf_types.h>
 
-unsigned int x86_family(unsigned int sig)
+static unsigned int __x86_family(unsigned int base_fam, unsigned int ext_fam)
 {
-	unsigned int x86;
-
-	x86 = (sig >> 8) & 0xf;
+	return (base_fam == 0xf) ? base_fam + ext_fam : base_fam;
+}
 
-	if (x86 == 0xf)
-		x86 += (sig >> 20) & 0xff;
+static unsigned int
+__x86_model(unsigned int family, unsigned int base_model, unsigned int ext_model)
+{
+	return (family >= 0x6) ? base_model | ext_model << 4 : base_model;
+}
 
-	return x86;
+unsigned int x86_family(unsigned int sig)
+{
+	return __x86_family((sig >> 8) & 0xf, (sig >> 20) & 0xff);
 }
 EXPORT_SYMBOL_GPL(x86_family);
 
-unsigned int x86_model(unsigned int sig)
+unsigned int cpuid_family(const struct leaf_0x1_0 *l)
 {
-	unsigned int fam, model;
-
-	fam = x86_family(sig);
-
-	model = (sig >> 4) & 0xf;
-
-	if (fam >= 0x6)
-		model += ((sig >> 16) & 0xf) << 4;
+	return __x86_family(l->base_family_id, l->ext_family);
+}
 
-	return model;
+unsigned int x86_model(unsigned int sig)
+{
+	return __x86_model(x86_family(sig), (sig >> 4) & 0xf, (sig >> 16) & 0xf);
 }
 EXPORT_SYMBOL_GPL(x86_model);
 
+unsigned int cpuid_model(const struct leaf_0x1_0 *l)
+{
+	return __x86_model(cpuid_family(l), l->base_model, l->ext_model);
+}
+
 unsigned int x86_stepping(unsigned int sig)
 {
 	return sig & 0xf;
-- 
2.49.0

[PATCH v3 27/44] x86/cpu: Use parsed CPUID(0x1)

[Ahmed S. Darwish]

Use parsed CPUID(0x1) access, instead of a direct CPUID query, at early
boot CPU detection code.

Beside the centralization benefits of the new CPUID model APIs, this
allows using the auto-generated <cpuid/leaf_types.h> leaf data types and
their full C99 bitfields instead of performing ugly bitwise operations on
CPUID register output.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/common.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b3408ae2b144..023613698b15 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -896,6 +896,7 @@ void get_cpu_vendor(struct cpuinfo_x86 *c)
 void cpu_detect(struct cpuinfo_x86 *c)
 {
 	const struct leaf_0x0_0 *l0 = cpuid_leaf(c, 0x0);
+	const struct leaf_0x1_0 *l1 = cpuid_leaf(c, 0x1);
 
 	c->cpuid_level = l0->max_std_leaf;
 	*(u32 *)&c->x86_vendor_id[0] = l0->cpu_vendorid_0;
@@ -903,17 +904,14 @@ void cpu_detect(struct cpuinfo_x86 *c)
 	*(u32 *)&c->x86_vendor_id[8] = l0->cpu_vendorid_2;
 
 	c->x86 = 4;
-	/* Intel-defined flags: level 0x00000001 */
-	if (c->cpuid_level >= 0x00000001) {
-		u32 junk, tfms, cap0, misc;
 
-		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
-		c->x86		= x86_family(tfms);
-		c->x86_model	= x86_model(tfms);
-		c->x86_stepping	= x86_stepping(tfms);
+	if (l1) {
+		c->x86		= cpuid_family(l1);
+		c->x86_model	= cpuid_model(l1);
+		c->x86_stepping	= l1->stepping;
 
-		if (cap0 & (1<<19)) {
-			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
+		if (l1->clflush) {
+			c->x86_clflush_size = l1->clflush_size * 8;
 			c->x86_cache_alignment = c->x86_clflush_size;
 		}
 	}
-- 
2.49.0

[PATCH v3 28/44] x86/cpuid: Parse CPUID(0x2)

[Ahmed S. Darwish]

Add CPUID(0x2) support to the CPUID parser.

Keep the leaf marked as invalid at the CPUID table if the whole leaf, or
all of its output registers, were malformed.

Note, the cpuid_leaf_0x2() logic at <cpuid/api.h> will be removed once
all the CPUID(0x2) call sites are transformed to the new CPUID model API.

References: fe78079ec07f ("x86/cpu: Introduce and use CPUID leaf 0x2 parsing helpers")
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/types.h |  1 +
 arch/x86/kernel/cpu/cpuid_parser.c | 41 +++++++++++++++++++++++++++---
 arch/x86/kernel/cpu/cpuid_parser.h |  1 +
 3 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index d0f0e6a8a457..7bbf0671cb95 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -215,6 +215,7 @@ struct cpuid_leaves {
 	/*         leaf		subleaf		count */
 	CPUID_LEAF(0x0,		0,		1);
 	CPUID_LEAF(0x1,		0,		1);
+	CPUID_LEAF(0x2,		0,		1);
 	CPUID_LEAF(0x80000000,	0,		1);
 };
 
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
index eb8975de497a..9bd68b150150 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.c
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -27,9 +27,40 @@ static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct cpuid_r
 		cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs);
 }
 
-/*
- * Leaf-independent parser code:
- */
+static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
+{
+	union leaf_0x2_regs *regs = (union leaf_0x2_regs *)output->regs;
+	struct leaf_0x2_0 *l = (struct leaf_0x2_0 *)output->regs;
+	int invalid_regs = 0;
+
+	/*
+	 * All Intel CPUs must report an iteration count of 1.  For broken hardware,
+	 * keep the leaf marked as invalid at the CPUID table.
+	 */
+	cpuid_read_subleaf(e->leaf, e->subleaf, l);
+	if (l->iteration_count != 0x01)
+		return;
+
+	/*
+	 * The most significant bit (MSB) of each CPUID(0x2) register must be clear.
+	 * If a register is malformed, replace its 1-byte descriptors with NULL.
+	 */
+	for (int i = 0; i < 4; i++) {
+		if (regs->reg[i].invalid) {
+			regs->regv[i] = 0;
+			invalid_regs++;
+		}
+	}
+
+	/*
+	 * If all of the CPUID(0x2) output registers were malformed, keep the leaf
+	 * marked as invalid at the CPUID table.
+	 */
+	if (invalid_regs == 4)
+		return;
+
+	output->info->nr_entries = 1;
+}
 
 static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
 {
@@ -54,6 +85,10 @@ static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struct cpui
 	output->info->nr_entries = 1;
 }
 
+/*
+ * Leaf-independent parser code:
+ */
+
 static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsigned int range)
 {
 	switch (range) {
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index 882e96b000ba..cf999e6a574d 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -96,6 +96,7 @@ struct cpuid_parse_entry {
 	/*		  Leaf		Subleaf		Reader function */		\
 	CPUID_PARSE_ENTRY(0x0,		0,		generic),			\
 	CPUID_PARSE_ENTRY(0x1,		0,		generic),			\
+	CPUID_PARSE_ENTRY(0x2,		0,		0x2),				\
 	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),
 
 extern const struct cpuid_parse_entry cpuid_common_parse_entries[];
-- 
2.49.0

[PATCH v3 29/44] x86/cpuid: Introduce parsed CPUID(0x2) API

[Ahmed S. Darwish]

Add a new iterator macro, for_each_parsed_cpuid_0x2_desc(), for
retrieving parsed CPUID(0x2) entries as 1-byte descriptors.

Unlike the existing for_each_cpuid_0x2_desc() macro, which operates on
directly retrieved CPUID data, the new one takes its input from the
centralized CPUID parser.  That is, it is expected to be used as:

    const struct leaf_0x2_table *desc;
    const struct cpuid_regs *regs;
    u8 *ptr;

    regs = cpuid_leaf_regs(c, 0x2);	// Parsed CPUID access
    for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
        ...
    }

which should replace the older method:

    const struct leaf_0x2_table *desc;
    union leaf_0x2_regs regs;
    u8 *ptr;

    cpuid_leaf_0x2(&regs);		// Direct CPUID access
    for_each_leaf_0x2_desc(regs, ptr, desc) {
        ...
    }

In the new macro, assert that the passed 'regs' is the same size as a
'union leaf_0x2_regs'.  This is necessary since the macro internally
casts 'regs' to that union in order to iterate over the CPUID(0x2) output
as a 1-byte array.

A size equivalence assert is used, instead of a typeof() check, to give
callers the freedom to either pass a 'struct cpuid_regs' pointer or a
'struct leaf_0x2_0' pointer, both as returned by the parsed CPUID API at
<cpuid/api.h>.  That size comparison matches what other kernel CPUID APIs
do; e.g. cpuid_read() and cpuid_read_subleaf() at <cpuid/api.h>.

Note, put the size equivalence check inside a GNU statement expression,
({..}), so that it can be placed inside the macro's loop initialization.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h | 43 ++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index dbc954e21b7e..6a0e766de565 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -544,6 +544,49 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
 	__cpuid_leaves_subleaf_info(&_cpuinfo->cpuid.leaves, _leaf, 0).nr_entries;\
 })
 
+/*
+ * Convenience leaf-specific functions (using parsed CPUID data):
+ */
+
+/*
+ * CPUID(0x2)
+ */
+
+/**
+ * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
+ * @_regs:   Leaf 0x2 register output, as returned by cpuid_leaf_regs()
+ * @_ptr:  u8 pointer, for macro internal use only
+ * @_desc:  Pointer to parsed descriptor information at each iteration
+ *
+ * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
+ * @_regs.  Provide the parsed information for each descriptor through @_desc.
+ *
+ * To handle cache-specific descriptors, switch on @_desc->c_type.  For TLB
+ * descriptors, switch on @_desc->t_type.
+ *
+ * Example usage for cache descriptors::
+ *
+ *	const struct leaf_0x2_table *desc;
+ *	struct cpuid_regs *regs;
+ *	u8 *ptr;
+ *
+ *	regs = cpuid_leaf_regs(c, 0x2);
+ *	if (!regs) {
+ *		// Handle error
+ *	}
+ *
+ *	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
+ *		switch (desc->c_type) {
+ *			...
+ *		}
+ *	}
+ */
+#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc)				\
+	for (({ static_assert(sizeof(*_regs) == sizeof(union leaf_0x2_regs)); }),	\
+	     _ptr = &((union leaf_0x2_regs *)(_regs))->desc[1];				\
+	     _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);\
+	     _ptr++)
+
 /*
  * CPUID parser exported APIs:
  */
-- 
2.49.0

[PATCH v3 30/44] x86/cpu: Use parsed CPUID(0x2)

[Ahmed S. Darwish]

Use parsed CPUID(0x2) access instead of direct CPUID queries.

Remove the max standard CPUID level check since the NULL check of
cpuid_leaf_regs()'s result is equivalent.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/intel.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 076eaa41b8c8..5eab9135b144 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -710,14 +710,14 @@ static void intel_tlb_lookup(const struct leaf_0x2_table *desc)
 static void intel_detect_tlb(struct cpuinfo_x86 *c)
 {
 	const struct leaf_0x2_table *desc;
-	union leaf_0x2_regs regs;
+	struct cpuid_regs *regs;
 	u8 *ptr;
 
-	if (c->cpuid_level < 2)
+	regs = cpuid_leaf_regs(c, 0x2);
+	if (!regs)
 		return;
 
-	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, desc)
+	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc)
 		intel_tlb_lookup(desc);
 }
 
-- 
2.49.0

[PATCH v3 31/44] x86/cacheinfo: Use parsed CPUID(0x2)

[Ahmed S. Darwish]

Use parsed CPUID(0x2) access instead of direct CPUID queries.

Remove the max standard CPUID level check since the NULL check of
cpuid_leaf_regs()'s result is equivalent.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index adfa7e8bb865..39cd6db4f702 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -382,14 +382,14 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 {
 	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0;
 	const struct leaf_0x2_table *desc;
-	union leaf_0x2_regs regs;
+	struct cpuid_regs *regs;
 	u8 *ptr;
 
-	if (c->cpuid_level < 2)
+	regs = cpuid_leaf_regs(c, 0x2);
+	if (!regs)
 		return;
 
-	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
 		switch (desc->c_type) {
 		case CACHE_L1_INST:	l1i += desc->c_size; break;
 		case CACHE_L1_DATA:	l1d += desc->c_size; break;
-- 
2.49.0

[PATCH v3 32/44] x86/cpuid: Remove direct CPUID(0x2) query API

[Ahmed S. Darwish]

All call sites at x86/cpu and x86/cacheinfo has been switched from direct
CPUID(0x2) access to parsed CPUID access.  Remove the direct CPUID(0x2)
query APIs at <asm/cpuid/api.h>:

    cpuid_leaf_0x2()
    for_each_cpuid_0x2_desc()

Rename the iterator macro:

    for_each_parsed_cpuid_0x2_desc()

back to:

    for_each_cpuid_0x2_desc()

since the "for_each_parsed_.." name and was just chosen to accommodate
the transition from direct CPUID(0x2) access to parsed access.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h | 75 ++------------------------------
 arch/x86/kernel/cpu/cacheinfo.c  |  2 +-
 arch/x86/kernel/cpu/intel.c      |  2 +-
 3 files changed, 5 insertions(+), 74 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 6a0e766de565..9f9c035a9e73 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -212,75 +212,6 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves)
 	return 0;
 }
 
-/*
- * CPUID(0x2) parsing:
- */
-
-/**
- * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output
- * @regs:	Output parameter
- *
- * Query CPUID(0x2) and store its output in @regs.  Force set any
- * invalid 1-byte descriptor returned by the hardware to zero (the NULL
- * cache/TLB descriptor) before returning it to the caller.
- *
- * Use for_each_cpuid_0x2_desc() to iterate over the register output in
- * parsed form.
- */
-static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
-{
-	cpuid_read(0x2, regs);
-
-	/*
-	 * All Intel CPUs must report an iteration count of 1.	In case
-	 * of bogus hardware, treat all returned descriptors as NULL.
-	 */
-	if (regs->desc[0] != 0x01) {
-		for (int i = 0; i < 4; i++)
-			regs->regv[i] = 0;
-		return;
-	}
-
-	/*
-	 * The most significant bit (MSB) of each register must be clear.
-	 * If a register is invalid, replace its descriptors with NULL.
-	 */
-	for (int i = 0; i < 4; i++) {
-		if (regs->reg[i].invalid)
-			regs->regv[i] = 0;
-	}
-}
-
-/**
- * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
- * @_regs:	CPUID(0x2) register output, as returned by cpuid_leaf_0x2()
- * @_ptr:	u8 pointer, for macro internal use only
- * @_desc:	Pointer to the parsed CPUID(0x2) descriptor at each iteration
- *
- * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
- * @_regs.  Provide the parsed information for each descriptor through @_desc.
- *
- * To handle cache-specific descriptors, switch on @_desc->c_type.  For TLB
- * descriptors, switch on @_desc->t_type.
- *
- * Example usage for cache descriptors::
- *
- *	const struct leaf_0x2_table *desc;
- *	union leaf_0x2_regs regs;
- *	u8 *ptr;
- *
- *	cpuid_leaf_0x2(&regs);
- *	for_each_cpuid_0x2_desc(regs, ptr, desc) {
- *		switch (desc->c_type) {
- *			...
- *		}
- *	}
- */
-#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc)				\
-	for (_ptr = &(_regs).desc[1];						\
-	     _ptr < &(_regs).desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);	\
-	     _ptr++)
-
 /*
  * CPUID(0x80000006) parsing:
  */
@@ -553,7 +484,7 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
  */
 
 /**
- * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
+ * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
  * @_regs:   Leaf 0x2 register output, as returned by cpuid_leaf_regs()
  * @_ptr:  u8 pointer, for macro internal use only
  * @_desc:  Pointer to parsed descriptor information at each iteration
@@ -575,13 +506,13 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
  *		// Handle error
  *	}
  *
- *	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
+ *	for_each_cpuid_0x2_desc(regs, ptr, desc) {
  *		switch (desc->c_type) {
  *			...
  *		}
  *	}
  */
-#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc)				\
+#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc)					\
 	for (({ static_assert(sizeof(*_regs) == sizeof(union leaf_0x2_regs)); }),	\
 	     _ptr = &((union leaf_0x2_regs *)(_regs))->desc[1];				\
 	     _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);\
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 39cd6db4f702..f837ccdec116 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 	if (!regs)
 		return;
 
-	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
+	for_each_cpuid_0x2_desc(regs, ptr, desc) {
 		switch (desc->c_type) {
 		case CACHE_L1_INST:	l1i += desc->c_size; break;
 		case CACHE_L1_DATA:	l1d += desc->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5eab9135b144..06c249110c8b 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 	if (!regs)
 		return;
 
-	for_each_parsed_cpuid_0x2_desc(regs, ptr, desc)
+	for_each_cpuid_0x2_desc(regs, ptr, desc)
 		intel_tlb_lookup(desc);
 }
 
-- 
2.49.0

[PATCH v3 33/44] x86/cpuid: Parse deterministic cache parameters CPUID leaves

[Ahmed S. Darwish]

Add CPUID parser logic for Intel CPUID(0x4) and AMD CPUID(0x8000001d).

Define a single cpuid_read_deterministic_cache() parsing function for
both leaves, as both have the same subleaf cache enumeration logic.

Introduce __define_cpuid_read_function() macro to avoid code duplication
between cpuid_read_generic(), the CPUID parser's default read function,
and the new cpuid_read_deterministic_cache() one.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/types.h |  2 ++
 arch/x86/kernel/cpu/cpuid_parser.c | 37 +++++++++++++++++++++++++-----
 arch/x86/kernel/cpu/cpuid_parser.h |  4 +++-
 3 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 7bbf0671cb95..89c399629e58 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -216,7 +216,9 @@ struct cpuid_leaves {
 	CPUID_LEAF(0x0,		0,		1);
 	CPUID_LEAF(0x1,		0,		1);
 	CPUID_LEAF(0x2,		0,		1);
+	CPUID_LEAF(0x4,		0,		8);
 	CPUID_LEAF(0x80000000,	0,		1);
+	CPUID_LEAF(0x8000001d,	0,		8);
 };
 
 /*
diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid_parser.c
index 9bd68b150150..3d0fa1c12ad0 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.c
+++ b/arch/x86/kernel/cpu/cpuid_parser.c
@@ -16,17 +16,42 @@
  * Leaf read functions:
  */
 
-/*
- * Default CPUID parser read function
+/**
+ * __define_cpuid_parser_read_function() - Generate a CPUID parser leaf read function
+ * @suffix:	Generated function name suffix (full name becomes: cpuid_read_@suffix())
+ * @_leaf_t:	Type to cast the CPUID query output storage pointer
+ * @_leaf:	Name of the CPUID query storage pointer
+ * @_break_c:	Condition to break the CPUID parsing loop, which may reference @_leaf, and
+ *		where @_leaf stores each iteration's CPUID query output.
  *
  * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read().
+ * Define a CPUID parser read function according to the requirements stated at
+ * 'struct cpuid_parse_entry'->read().
  */
-static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
-{
-	for (int i = 0; i < e->maxcnt; i++, output->regs++, output->info->nr_entries++)
-		cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs);
+#define __define_cpuid_parser_read_function(suffix, _leaf_t, _leaf, _break_c)			\
+static void											\
+cpuid_read_##suffix(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)	\
+{												\
+	struct _leaf_t *_leaf = (struct _leaf_t *)output->regs;					\
+												\
+	for (int i = 0; i < e->maxcnt; i++, _leaf++, output->info->nr_entries++) {		\
+		cpuid_read_subleaf(e->leaf, e->subleaf + i, _leaf);				\
+		if (_break_c)									\
+			break;									\
+	}											\
 }
 
+/*
+ * Default CPUID parser read function
+ */
+__define_cpuid_parser_read_function(generic, cpuid_regs, ignored, false);
+
+/*
+ * Shared read function for Intel CPUID(0x4) and AMD CPUID(0x8000001d), as both have
+ * the same subleaf enumeration logic and registers output format.
+ */
+__define_cpuid_parser_read_function(deterministic_cache, leaf_0x4_0, l, l->cache_type == 0);
+
 static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid_read_output *output)
 {
 	union leaf_0x2_regs *regs = (union leaf_0x2_regs *)output->regs;
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index cf999e6a574d..be4ef64c48b6 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -97,7 +97,9 @@ struct cpuid_parse_entry {
 	CPUID_PARSE_ENTRY(0x0,		0,		generic),			\
 	CPUID_PARSE_ENTRY(0x1,		0,		generic),			\
 	CPUID_PARSE_ENTRY(0x2,		0,		0x2),				\
-	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),
+	CPUID_PARSE_ENTRY(0x4,		0,		deterministic_cache),		\
+	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),			\
+	CPUID_PARSE_ENTRY(0x8000001d,	0,		deterministic_cache),
 
 extern const struct cpuid_parse_entry cpuid_common_parse_entries[];
 extern const int cpuid_common_parse_entries_size;
-- 
2.49.0

[PATCH v3 34/44] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code

[Ahmed S. Darwish]

Prepare the CPUID(0x4) cache topology code for using parsed CPUID APIs
instead of invoking direct CPUID queries.

Since such an API requires a 'struct cpuinfo_x86' reference, trickle it
from the <linux/cacheinfo.h>'s populate_cache_leaves() x86 implementation
down to fill_cpuid4_info() and its Intel-specific CPUID(0x4) code.

No functional change intended.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://lore.kernel.org/lkml/aBnEBbDATdE2LTGU@gmail.com
---
 arch/x86/kernel/cpu/cacheinfo.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index f837ccdec116..0ed5dd6d29ef 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -252,7 +252,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4)
 	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
 }
 
-static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4)
+static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, struct _cpuid4_info *id4)
 {
 	union _cpuid4_leaf_eax eax;
 	union _cpuid4_leaf_ebx ebx;
@@ -264,13 +264,13 @@ static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4)
 	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
 }
 
-static int fill_cpuid4_info(int index, struct _cpuid4_info *id4)
+static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
 {
 	u8 cpu_vendor = boot_cpu_data.x86_vendor;
 
 	return (cpu_vendor == X86_VENDOR_AMD || cpu_vendor == X86_VENDOR_HYGON) ?
 		amd_fill_cpuid4_info(index, id4) :
-		intel_fill_cpuid4_info(index, id4);
+		intel_fill_cpuid4_info(c, index, id4);
 }
 
 static int find_num_cache_leaves(struct cpuinfo_x86 *c)
@@ -434,7 +434,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c)
 		struct _cpuid4_info id4 = {};
 		int ret;
 
-		ret = intel_fill_cpuid4_info(i, &id4);
+		ret = intel_fill_cpuid4_info(c, i, &id4);
 		if (ret < 0)
 			continue;
 
@@ -618,13 +618,14 @@ int populate_cache_leaves(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 	struct cacheinfo *ci = this_cpu_ci->info_list;
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	u8 cpu_vendor = boot_cpu_data.x86_vendor;
 	struct amd_northbridge *nb = NULL;
 	struct _cpuid4_info id4 = {};
 	int idx, ret;
 
 	for (idx = 0; idx < this_cpu_ci->num_leaves; idx++) {
-		ret = fill_cpuid4_info(idx, &id4);
+		ret = fill_cpuid4_info(c, idx, &id4);
 		if (ret)
 			return ret;
 
-- 
2.49.0

[PATCH v3 35/44] x86/cacheinfo: Use parsed CPUID(0x4)

[Ahmed S. Darwish]

Refactor the Intel CPUID(0x4) cacheinfo logic to use parsed CPUID access
instead of issuing direct CPUID queries.

Use the parsed CPUID access macro:

    cpuid_subleaf_count(c, 0x4)

to determine the number of Intel CPUID(0x4) cache leaves instead of
calling find_num_cache_leaves(), which internally issues direct CPUID
queries.

Since find_num_cache_leaves() is no longer needed for Intel code paths,
make it AMD-specific.  Rename it to amd_find_num_cache_leaves() and
remove its Intel CPUID(0x4) logic.  Adjust the AMD paths accordingly.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 31 ++++++++++++++-----------------
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 0ed5dd6d29ef..07f0883f9fbe 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -252,16 +252,14 @@ static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4)
 	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
 }
 
-static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, struct _cpuid4_info *id4)
+static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
 {
-	union _cpuid4_leaf_eax eax;
-	union _cpuid4_leaf_ebx ebx;
-	union _cpuid4_leaf_ecx ecx;
-	u32 ignored;
-
-	cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored);
+	const struct cpuid_regs *regs = cpuid_subleaf_index_regs(c, 0x4, index);
 
-	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
+	return cpuid4_info_fill_done(id4,
+				     (union _cpuid4_leaf_eax)(regs->eax),
+				     (union _cpuid4_leaf_ebx)(regs->ebx),
+				     (union _cpuid4_leaf_ecx)(regs->ecx));
 }
 
 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
@@ -273,17 +271,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_inf
 		intel_fill_cpuid4_info(c, index, id4);
 }
 
-static int find_num_cache_leaves(struct cpuinfo_x86 *c)
+static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c)
 {
-	unsigned int eax, ebx, ecx, edx, op;
 	union _cpuid4_leaf_eax cache_eax;
+	unsigned int eax, ebx, ecx, edx;
 	int i = -1;
 
-	/* Do a CPUID(op) loop to calculate num_cache_leaves */
-	op = (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) ? 0x8000001d : 4;
+	/* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */
 	do {
 		++i;
-		cpuid_count(op, i, &eax, &ebx, &ecx, &edx);
+		cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx);
 		cache_eax.full = eax;
 	} while (cache_eax.split.type != CTYPE_NULL);
 	return i;
@@ -313,7 +310,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
 		 * of threads sharing the L3 cache.
 		 */
 		u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
-		u32 llc_index = find_num_cache_leaves(c) - 1;
+		u32 llc_index = amd_find_num_cache_leaves(c) - 1;
 
 		cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
 		if (eax)
@@ -344,7 +341,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);
 
 	if (boot_cpu_has(X86_FEATURE_TOPOEXT))
-		ci->num_leaves = find_num_cache_leaves(c);
+		ci->num_leaves = amd_find_num_cache_leaves(c);
 	else if (c->extended_cpuid_level >= 0x80000006)
 		ci->num_leaves = (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3;
 }
@@ -353,7 +350,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
 {
 	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);
 
-	ci->num_leaves = find_num_cache_leaves(c);
+	ci->num_leaves = amd_find_num_cache_leaves(c);
 }
 
 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3,
@@ -425,7 +422,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c)
 	 * that the number of leaves has been previously initialized.
 	 */
 	if (!ci->num_leaves)
-		ci->num_leaves = find_num_cache_leaves(c);
+		ci->num_leaves = cpuid_subleaf_count(c, 0x4);
 
 	if (!ci->num_leaves)
 		return false;
-- 
2.49.0

[PATCH v3 36/44] x86/cacheinfo: Use parsed CPUID(0x8000001d)

[Ahmed S. Darwish]

Refactor the AMD CPUID(0x8000001d) cacheinfo logic to use the parsed
CPUID API instead of issuing direct CPUID queries.

Beside CPUID data centralization benefits, this allows using the
auto-generated <cpuid/leaf_types.h> 'struct cpuid_0x8000001d_0' data type
with its full C99 bitfields instead of doing ugly bitwise operations.

Since parsed CPUID access requires a 'struct cpuinfo_x86' reference,
trickle it down to relevant functions.

Use the parsed CPUID API:

    cpuid_subleaf_count(c, 0x8000001d)

to find the number of cache leaves, thus replacing
amd_find_num_cache_leaves() and its direct CPUID queries.  Drop that
function entirely as it is no longer needed.

For now, keep using the 'union _cpuid4_leaf_eax/ebx/ecx' structures as
they are required by the AMD CPUID(0x4) emulation code paths.  A follow
up commit will replace them with <cpuid/leaf_types.h> equivalents.

Note, for below code:

    cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
    if (eax)
        num_sharing_cache = ((eax >> 14) & 0xfff) + 1;

    if (num_sharing_cache) {
        int index_msb = get_count_order(num_sharing_cache);
        ...
    }

it is replaced with:

    const struct leaf_0x8000001d_0 *leaf =
        cpuid_subleaf_index(c, 0x8000001d, llc_index);

    if (leaf) {
        int index_msb = get_count_order(l->num_threads_sharing + 1);
        ...
    }

The "if (leaf)" check is sufficient since the parsed CPUID API returns
NULL if the leaf is out of range (> max CPU extended leaf) or if the
'llc_index' is out of range.  An out of range LLC index is equivalent to
"EAX.cache_type == 0" in the original code, making the logic match.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 47 +++++++++++----------------------
 1 file changed, 16 insertions(+), 31 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 07f0883f9fbe..05a3fbd0d849 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -237,16 +237,19 @@ static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_leaf_ea
 	return 0;
 }
 
-static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4)
+static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
 {
 	union _cpuid4_leaf_eax eax;
 	union _cpuid4_leaf_ebx ebx;
 	union _cpuid4_leaf_ecx ecx;
-	u32 ignored;
 
-	if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
-		cpuid_count(0x8000001d, index, &eax.full, &ebx.full, &ecx.full, &ignored);
-	else
+	if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+		const struct cpuid_regs *regs = cpuid_subleaf_index_regs(c, 0x8000001d, index);
+
+		eax.full = regs->eax;
+		ebx.full = regs->ebx;
+		ecx.full = regs->ecx;
+	} else
 		legacy_amd_cpuid4(index, &eax, &ebx, &ecx);
 
 	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
@@ -267,25 +270,10 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_inf
 	u8 cpu_vendor = boot_cpu_data.x86_vendor;
 
 	return (cpu_vendor == X86_VENDOR_AMD || cpu_vendor == X86_VENDOR_HYGON) ?
-		amd_fill_cpuid4_info(index, id4) :
+		amd_fill_cpuid4_info(c, index, id4) :
 		intel_fill_cpuid4_info(c, index, id4);
 }
 
-static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c)
-{
-	union _cpuid4_leaf_eax cache_eax;
-	unsigned int eax, ebx, ecx, edx;
-	int i = -1;
-
-	/* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */
-	do {
-		++i;
-		cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx);
-		cache_eax.full = eax;
-	} while (cache_eax.split.type != CTYPE_NULL);
-	return i;
-}
-
 /*
  * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist.
  */
@@ -309,15 +297,12 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
 		 * Newer families: LLC ID is calculated from the number
 		 * of threads sharing the L3 cache.
 		 */
-		u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
-		u32 llc_index = amd_find_num_cache_leaves(c) - 1;
-
-		cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
-		if (eax)
-			num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
+		u32 llc_index = cpuid_subleaf_count(c, 0x8000001d) - 1;
+		const struct leaf_0x8000001d_0 *leaf =
+			cpuid_subleaf_index(c, 0x8000001d, llc_index);
 
-		if (num_sharing_cache) {
-			int index_msb = get_count_order(num_sharing_cache);
+		if (leaf) {
+			int index_msb = get_count_order(leaf->num_threads_sharing + 1);
 
 			c->topo.llc_id = c->topo.apicid >> index_msb;
 		}
@@ -341,7 +326,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);
 
 	if (boot_cpu_has(X86_FEATURE_TOPOEXT))
-		ci->num_leaves = amd_find_num_cache_leaves(c);
+		ci->num_leaves = cpuid_subleaf_count(c, 0x8000001d);
 	else if (c->extended_cpuid_level >= 0x80000006)
 		ci->num_leaves = (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3;
 }
@@ -350,7 +335,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
 {
 	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);
 
-	ci->num_leaves = amd_find_num_cache_leaves(c);
+	ci->num_leaves = cpuid_subleaf_count(c, 0x8000001d);
 }
 
 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3,
-- 
2.49.0

[PATCH v3 37/44] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006)

[Ahmed S. Darwish]

Parse AMD cacheinfo CPUID(0x80000005) and CPUID(0x80000006), if available,
using the generic CPUID parser read function cpuid_read_generic().

The x86/cacheinfo AMD CPUID(0x4)-emulation logic will be swithced next to
the parsed CPUID table APIs instead of invoking direct CPUID queries.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/types.h | 2 ++
 arch/x86/kernel/cpu/cpuid_parser.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index 89c399629e58..63d2569e2821 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -218,6 +218,8 @@ struct cpuid_leaves {
 	CPUID_LEAF(0x2,		0,		1);
 	CPUID_LEAF(0x4,		0,		8);
 	CPUID_LEAF(0x80000000,	0,		1);
+	CPUID_LEAF(0x80000005,	0,		1);
+	CPUID_LEAF(0x80000006,	0,		1);
 	CPUID_LEAF(0x8000001d,	0,		8);
 };
 
diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid_parser.h
index be4ef64c48b6..e4b34f0946ec 100644
--- a/arch/x86/kernel/cpu/cpuid_parser.h
+++ b/arch/x86/kernel/cpu/cpuid_parser.h
@@ -99,6 +99,8 @@ struct cpuid_parse_entry {
 	CPUID_PARSE_ENTRY(0x2,		0,		0x2),				\
 	CPUID_PARSE_ENTRY(0x4,		0,		deterministic_cache),		\
 	CPUID_PARSE_ENTRY(0x80000000,	0,		0x80000000),			\
+	CPUID_PARSE_ENTRY(0x80000005,	0,		generic),			\
+	CPUID_PARSE_ENTRY(0x80000006,	0,		generic),			\
 	CPUID_PARSE_ENTRY(0x8000001d,	0,		deterministic_cache),
 
 extern const struct cpuid_parse_entry cpuid_common_parse_entries[];
-- 
2.49.0

[PATCH v3 38/44] x86/cacheinfo: Use auto-generated data types

[Ahmed S. Darwish]

For the AMD CPUID(0x4) emulation logic, use the auto-generated
<cpuid/leaf_types.h> data type:

    struct leaf_0x4_0

instead of the manually-defined:

    union _cpuid4_leaf_{eax,ebx,ecx}

ones.  Remove such unions entirely as they are no longer used.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db
---
 arch/x86/kernel/cpu/cacheinfo.c | 130 +++++++++++---------------------
 1 file changed, 42 insertions(+), 88 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 05a3fbd0d849..f0540cba4bd4 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -41,39 +41,8 @@ enum _cache_type {
 	CTYPE_UNIFIED	= 3
 };
 
-union _cpuid4_leaf_eax {
-	struct {
-		enum _cache_type	type			:5;
-		unsigned int		level			:3;
-		unsigned int		is_self_initializing	:1;
-		unsigned int		is_fully_associative	:1;
-		unsigned int		reserved		:4;
-		unsigned int		num_threads_sharing	:12;
-		unsigned int		num_cores_on_die	:6;
-	} split;
-	u32 full;
-};
-
-union _cpuid4_leaf_ebx {
-	struct {
-		unsigned int		coherency_line_size	:12;
-		unsigned int		physical_line_partition	:10;
-		unsigned int		ways_of_associativity	:10;
-	} split;
-	u32 full;
-};
-
-union _cpuid4_leaf_ecx {
-	struct {
-		unsigned int		number_of_sets		:32;
-	} split;
-	u32 full;
-};
-
 struct _cpuid4_info {
-	union _cpuid4_leaf_eax eax;
-	union _cpuid4_leaf_ebx ebx;
-	union _cpuid4_leaf_ecx ecx;
+	struct leaf_0x4_0 regs;
 	unsigned int id;
 	unsigned long size;
 };
@@ -148,17 +117,14 @@ static const unsigned short assocs[] = {
 static const unsigned char levels[] = { 1, 1, 2, 3 };
 static const unsigned char types[]  = { 1, 2, 3, 3 };
 
-static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
-			      union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx)
+static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs)
 {
 	unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb;
 	union l1_cache l1i, l1d, *l1;
 	union l2_cache l2;
 	union l3_cache l3;
 
-	eax->full = 0;
-	ebx->full = 0;
-	ecx->full = 0;
+	*regs = (struct leaf_0x4_0){ };
 
 	cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
 	cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
@@ -204,65 +170,53 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
 		return;
 	}
 
-	eax->split.is_self_initializing		= 1;
-	eax->split.type				= types[index];
-	eax->split.level			= levels[index];
-	eax->split.num_threads_sharing		= 0;
-	eax->split.num_cores_on_die		= topology_num_cores_per_package();
+	regs->cache_self_init		= 1;
+	regs->cache_type		= types[index];
+	regs->cache_level		= levels[index];
+	regs->num_threads_sharing	= 0;
+	regs->num_cores_on_die		= topology_num_cores_per_package();
 
 	if (assoc == AMD_CPUID4_FULLY_ASSOCIATIVE)
-		eax->split.is_fully_associative = 1;
+		regs->fully_associative	= 1;
 
-	ebx->split.coherency_line_size		= line_size - 1;
-	ebx->split.ways_of_associativity	= assoc - 1;
-	ebx->split.physical_line_partition	= lines_per_tag - 1;
-	ecx->split.number_of_sets		= (size_in_kb * 1024) / line_size /
-		(ebx->split.ways_of_associativity + 1) - 1;
+	regs->cache_linesize		= line_size - 1;
+	regs->cache_nways		= assoc - 1;
+	regs->cache_npartitions		= lines_per_tag - 1;
+	regs->cache_nsets		= (size_in_kb * 1024) / line_size /
+		(regs->cache_nways + 1) - 1;
 }
 
-static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_leaf_eax eax,
-				 union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx)
+static int cpuid4_info_fill_done(struct _cpuid4_info *id4, const struct leaf_0x4_0 *regs)
 {
-	if (eax.split.type == CTYPE_NULL)
+	if (regs->cache_type == CTYPE_NULL)
 		return -EIO;
 
-	id4->eax = eax;
-	id4->ebx = ebx;
-	id4->ecx = ecx;
-	id4->size = (ecx.split.number_of_sets          + 1) *
-		    (ebx.split.coherency_line_size     + 1) *
-		    (ebx.split.physical_line_partition + 1) *
-		    (ebx.split.ways_of_associativity   + 1);
+	id4->regs = *regs;
+	id4->size = (regs->cache_nsets	     + 1) *
+		    (regs->cache_linesize    + 1) *
+		    (regs->cache_npartitions + 1) *
+		    (regs->cache_nways	     + 1);
 
 	return 0;
 }
 
 static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
 {
-	union _cpuid4_leaf_eax eax;
-	union _cpuid4_leaf_ebx ebx;
-	union _cpuid4_leaf_ecx ecx;
+	struct leaf_0x4_0 regs;
 
-	if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
-		const struct cpuid_regs *regs = cpuid_subleaf_index_regs(c, 0x8000001d, index);
-
-		eax.full = regs->eax;
-		ebx.full = regs->ebx;
-		ecx.full = regs->ecx;
-	} else
-		legacy_amd_cpuid4(index, &eax, &ebx, &ecx);
+	if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+		regs = *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index);
+	else
+		legacy_amd_cpuid4(index, &regs);
 
-	return cpuid4_info_fill_done(id4, eax, ebx, ecx);
+	return cpuid4_info_fill_done(id4, &regs);
 }
 
 static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
 {
-	const struct cpuid_regs *regs = cpuid_subleaf_index_regs(c, 0x4, index);
+	const struct leaf_0x4_0 *regs = cpuid_subleaf_index(c, 0x4, index);
 
-	return cpuid4_info_fill_done(id4,
-				     (union _cpuid4_leaf_eax)(regs->eax),
-				     (union _cpuid4_leaf_ebx)(regs->ebx),
-				     (union _cpuid4_leaf_ecx)(regs->ecx));
+	return cpuid4_info_fill_done(id4, regs);
 }
 
 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_info *id4)
@@ -388,7 +342,7 @@ static unsigned int calc_cache_topo_id(struct cpuinfo_x86 *c, const struct _cpui
 	unsigned int num_threads_sharing;
 	int index_msb;
 
-	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
+	num_threads_sharing = 1 + id4->regs.num_threads_sharing;
 	index_msb = get_count_order(num_threads_sharing);
 	return c->topo.apicid & ~((1 << index_msb) - 1);
 }
@@ -420,11 +374,11 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c)
 		if (ret < 0)
 			continue;
 
-		switch (id4.eax.split.level) {
+		switch (id4.regs.cache_level) {
 		case 1:
-			if (id4.eax.split.type == CTYPE_DATA)
+			if (id4.regs.cache_type == CTYPE_DATA)
 				l1d = id4.size / 1024;
-			else if (id4.eax.split.type == CTYPE_INST)
+			else if (id4.regs.cache_type == CTYPE_INST)
 				l1i = id4.size / 1024;
 			break;
 		case 2:
@@ -485,7 +439,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
 	} else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
 		unsigned int apicid, nshared, first, last;
 
-		nshared = id4->eax.split.num_threads_sharing + 1;
+		nshared = id4->regs.num_threads_sharing + 1;
 		apicid = cpu_data(cpu).topo.apicid;
 		first = apicid - (apicid % nshared);
 		last = first + nshared - 1;
@@ -532,7 +486,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int index,
 	}
 
 	ci = this_cpu_ci->info_list + index;
-	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
+	num_threads_sharing = 1 + id4->regs.num_threads_sharing;
 
 	cpumask_set_cpu(cpu, &ci->shared_cpu_map);
 	if (num_threads_sharing == 1)
@@ -559,13 +513,13 @@ static void ci_info_init(struct cacheinfo *ci, const struct _cpuid4_info *id4,
 {
 	ci->id				= id4->id;
 	ci->attributes			= CACHE_ID;
-	ci->level			= id4->eax.split.level;
-	ci->type			= cache_type_map[id4->eax.split.type];
-	ci->coherency_line_size		= id4->ebx.split.coherency_line_size + 1;
-	ci->ways_of_associativity	= id4->ebx.split.ways_of_associativity + 1;
+	ci->level			= id4->regs.cache_level;
+	ci->type			= cache_type_map[id4->regs.cache_type];
+	ci->coherency_line_size		= id4->regs.cache_linesize + 1;
+	ci->ways_of_associativity	= id4->regs.cache_nways + 1;
 	ci->size			= id4->size;
-	ci->number_of_sets		= id4->ecx.split.number_of_sets + 1;
-	ci->physical_line_partition	= id4->ebx.split.physical_line_partition + 1;
+	ci->number_of_sets		= id4->regs.cache_nsets + 1;
+	ci->physical_line_partition	= id4->regs.cache_npartitions + 1;
 	ci->priv			= nb;
 }
 
@@ -591,7 +545,7 @@ static void get_cache_id(int cpu, struct _cpuid4_info *id4)
 	unsigned long num_threads_sharing;
 	int index_msb;
 
-	num_threads_sharing = 1 + id4->eax.split.num_threads_sharing;
+	num_threads_sharing = 1 + id4->regs.num_threads_sharing;
 	index_msb = get_count_order(num_threads_sharing);
 	id4->id = c->topo.apicid >> index_msb;
 }
-- 
2.49.0

[PATCH v3 39/44] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006)

[Ahmed S. Darwish]

For the AMD CPUID(0x4)-emulation logic, use parsed CPUID(0x80000005) and
CPUID(0x80000006) APID access instead of invoking direct CPUID queries.

Beside centralizing CPUID access, this allows using the auto-generated
<cpuid/leaf_types.h> 'struct leaf_0x80000005_0' and 'struct
leaf_0x80000006_0' data types.

Remove the 'union {l1,l2,l3}_cache' definitions as they are no longer
needed.

Note, the expression:

    ci->num_leaves = (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3;

is replaced with:

    ci->num_leaves = cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3;

which is the same logic, since the 'l3_assoc' bitfield is 4 bits wide at
EDX offset 12.  Per AMD manuals, an L3 associativity of zero implies the
absence of an L3 cache on the CPU.

While at it, separate the 'Fallback AMD CPUID(0x4) emulation' comment
from the '@AMD_L2_L3_INVALID_ASSOC' one, since the former acts as a
source code section header.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 105 ++++++++++++--------------------
 1 file changed, 40 insertions(+), 65 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index f0540cba4bd4..de8e7125eedd 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -56,47 +56,17 @@ static const enum cache_type cache_type_map[] = {
 };
 
 /*
- * Fallback AMD CPUID(0x4) emulation
+ * Fallback AMD CPUID(0x4) emulation:
  * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d)
- *
+ */
+
+/*
  * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache should
  * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006).
  */
-
 #define AMD_CPUID4_FULLY_ASSOCIATIVE	0xffff
 #define AMD_L2_L3_INVALID_ASSOC		0x9
 
-union l1_cache {
-	struct {
-		unsigned line_size	:8;
-		unsigned lines_per_tag	:8;
-		unsigned assoc		:8;
-		unsigned size_in_kb	:8;
-	};
-	unsigned int val;
-};
-
-union l2_cache {
-	struct {
-		unsigned line_size	:8;
-		unsigned lines_per_tag	:4;
-		unsigned assoc		:4;
-		unsigned size_in_kb	:16;
-	};
-	unsigned int val;
-};
-
-union l3_cache {
-	struct {
-		unsigned line_size	:8;
-		unsigned lines_per_tag	:4;
-		unsigned assoc		:4;
-		unsigned res		:2;
-		unsigned size_encoded	:14;
-	};
-	unsigned int val;
-};
-
 /* L2/L3 associativity mapping */
 static const unsigned short assocs[] = {
 	[1]		= 1,
@@ -117,50 +87,52 @@ static const unsigned short assocs[] = {
 static const unsigned char levels[] = { 1, 1, 2, 3 };
 static const unsigned char types[]  = { 1, 2, 3, 3 };
 
-static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs)
+static void legacy_amd_cpuid4(struct cpuinfo_x86 *c, int index, struct leaf_0x4_0 *regs)
 {
-	unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb;
-	union l1_cache l1i, l1d, *l1;
-	union l2_cache l2;
-	union l3_cache l3;
+	const struct leaf_0x80000005_0 *el5 = cpuid_leaf(c, 0x80000005);
+	const struct leaf_0x80000006_0 *el6 = cpuid_leaf(c, 0x80000006);
+	const struct cpuid_regs *el5_raw = (const struct cpuid_regs *)el5;
+	unsigned int line_size, lines_per_tag, assoc, size_in_kb;
 
 	*regs = (struct leaf_0x4_0){ };
 
-	cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
-	cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
-
-	l1 = &l1d;
 	switch (index) {
-	case 1:
-		l1 = &l1i;
-		fallthrough;
 	case 0:
-		if (!l1->val)
+		if (!el5 || !el5_raw->ecx)
 			return;
 
-		assoc		= (l1->assoc == 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->assoc;
-		line_size	= l1->line_size;
-		lines_per_tag	= l1->lines_per_tag;
-		size_in_kb	= l1->size_in_kb;
+		assoc		= el5->l1_dcache_assoc;
+		line_size	= el5->l1_dcache_line_size;
+		lines_per_tag	= el5->l1_dcache_nlines;
+		size_in_kb	= el5->l1_dcache_size_kb;
+		break;
+	case 1:
+		if (!el5 || !el5_raw->edx)
+			return;
+
+		assoc		= el5->l1_icache_assoc;
+		line_size	= el5->l1_icache_line_size;
+		lines_per_tag	= el5->l1_icache_nlines;
+		size_in_kb	= el5->l1_icache_size_kb;
 		break;
 	case 2:
-		if (!l2.assoc || l2.assoc == AMD_L2_L3_INVALID_ASSOC)
+		if (!el6 || !el6->l2_assoc || el6->l2_assoc == AMD_L2_L3_INVALID_ASSOC)
 			return;
 
 		/* Use x86_cache_size as it might have K7 errata fixes */
-		assoc		= assocs[l2.assoc];
-		line_size	= l2.line_size;
-		lines_per_tag	= l2.lines_per_tag;
+		assoc		= assocs[el6->l2_assoc];
+		line_size	= el6->l2_line_size;
+		lines_per_tag	= el6->l2_nlines;
 		size_in_kb	= __this_cpu_read(cpu_info.x86_cache_size);
 		break;
 	case 3:
-		if (!l3.assoc || l3.assoc == AMD_L2_L3_INVALID_ASSOC)
+		if (!el6 || !el6->l3_assoc || el6->l3_assoc == AMD_L2_L3_INVALID_ASSOC)
 			return;
 
-		assoc		= assocs[l3.assoc];
-		line_size	= l3.line_size;
-		lines_per_tag	= l3.lines_per_tag;
-		size_in_kb	= l3.size_encoded * 512;
+		assoc		= assocs[el6->l3_assoc];
+		line_size	= el6->l3_line_size;
+		lines_per_tag	= el6->l3_nlines;
+		size_in_kb	= el6->l3_size_range * 512;
 		if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
 			size_in_kb	= size_in_kb >> 1;
 			assoc		= assoc >> 1;
@@ -170,6 +142,10 @@ static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs)
 		return;
 	}
 
+	/* For L1d and L1i caches, 0xff is the full associativity marker */
+	if ((index == 0 || index == 1) && assoc == 0xff)
+		assoc = AMD_CPUID4_FULLY_ASSOCIATIVE;
+
 	regs->cache_self_init		= 1;
 	regs->cache_type		= types[index];
 	regs->cache_level		= levels[index];
@@ -207,7 +183,7 @@ static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4
 	if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
 		regs = *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index);
 	else
-		legacy_amd_cpuid4(index, &regs);
+		legacy_amd_cpuid4(c, index, &regs);
 
 	return cpuid4_info_fill_done(id4, &regs);
 }
@@ -279,10 +255,9 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 {
 	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(c->cpu_index);
 
-	if (boot_cpu_has(X86_FEATURE_TOPOEXT))
-		ci->num_leaves = cpuid_subleaf_count(c, 0x8000001d);
-	else if (c->extended_cpuid_level >= 0x80000006)
-		ci->num_leaves = (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3;
+	ci->num_leaves = boot_cpu_has(X86_FEATURE_TOPOEXT) ?
+		cpuid_subleaf_count(c, 0x8000001d) :
+		cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3;
 }
 
 void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
-- 
2.49.0

[PATCH v3 40/44] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference

[Ahmed S. Darwish]

Prepare cpuid_amd_hygon_has_l3_cache(), which is internally a
CPUID(0x80000006) call site, for using the parsed CPUID API instead of
invoking direct CPUID queries.

Since such an API requires a 'struct cpuinfo_x86' reference, trickle it
down from the start of the amd_nb initcall.

Note, accessing the CPUID tables at initcall_5 using this_cpu_ptr()
should be safe, since the 'struct cpuinfo_x86' per-CPU presentation is
finalized at arch/x86/kernel/cpu/common.c :: arch_cpu_finalize_init().
Meanwhile, at kernel init/main.c, do_initcalls() are done much later.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/amd_nb.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index c1acead6227a..a8809778b208 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -16,6 +16,7 @@
 
 #include <asm/amd/nb.h>
 #include <asm/cpuid/api.h>
+#include <asm/processor.h>
 
 static u32 *flush_words;
 
@@ -58,7 +59,7 @@ struct amd_northbridge *node_to_amd_nb(int node)
 }
 EXPORT_SYMBOL_GPL(node_to_amd_nb);
 
-static int amd_cache_northbridges(void)
+static int amd_cache_northbridges(struct cpuinfo_x86 *c)
 {
 	struct amd_northbridge *nb;
 	u16 i;
@@ -315,11 +316,13 @@ static __init void fix_erratum_688(void)
 
 static __init int init_amd_nbs(void)
 {
+	struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
+
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 		return 0;
 
-	amd_cache_northbridges();
+	amd_cache_northbridges(c);
 	amd_cache_gart();
 
 	fix_erratum_688();
-- 
2.49.0

[PATCH v3 41/44] x86/cpu: <asm/processor.h>: Do not include CPUID API header

[Ahmed S. Darwish]

<asm/processor.h> includes the CPUID API header <asm/cpuid/api.h>, but
all what it actually needs are data types from <asm/cpuid/types.h>.

Modify the header to include <asm/cpuid/types.h> instead.

Note, this allows the CPUID API header to include <asm/processor.h> next,
without inducing a circular dependency.  This will be needed by the
upcoming centralized CPUID model APIs.

Note, a large number of call sites were already using the CPUID APIs
without including <asm/cpuid/api.h>.  They directly or indirectly
included <asm/processor.h>, which included the CPUID API header.  Such
call sites have been modified, by parent commits, to explicitly include
the CPUID API header instead.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/processor.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index b5d90b60191b..88f8ee33bfca 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -16,7 +16,7 @@ struct vm86;
 #include <uapi/asm/sigcontext.h>
 #include <asm/current.h>
 #include <asm/cpufeatures.h>
-#include <asm/cpuid/api.h>
+#include <asm/cpuid/types.h>
 #include <asm/page.h>
 #include <asm/pgtable_types.h>
 #include <asm/percpu.h>
-- 
2.49.0

[PATCH v3 42/44] x86/cpuid: Use parsed CPUID(0x80000006)

[Ahmed S. Darwish]

For cpuid_amd_hygon_has_l3_cache(), use parsed CPUID access instead of a
direct CPUID query.  The new API offers centralization benefits and
avoids bit fiddling at call sites.

For testing L3 cache availability, just check if the EDX.l3_assoc output
is not zero.  Per AMD manuals, an L3 associativity of zero implies the
absence of an L3 cache on the CPU.

Note, since this function is now using parsed CPUID API, move it under
the <cpuid/api.h> section: 'Convenience leaf-specific functions (using
parsed CPUID data)'

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h | 18 +++++++++---------
 arch/x86/kernel/amd_nb.c         |  2 +-
 arch/x86/kernel/cpu/cacheinfo.c  |  6 +++---
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 9f9c035a9e73..92366de5e490 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -212,15 +212,6 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves)
 	return 0;
 }
 
-/*
- * CPUID(0x80000006) parsing:
- */
-
-static inline bool cpuid_amd_hygon_has_l3_cache(void)
-{
-	return cpuid_edx(0x80000006);
-}
-
 /*
  * 'struct cpuid_leaves' accessors:
  *
@@ -518,6 +509,15 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void)
 	     _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);\
 	     _ptr++)
 
+/*
+ * CPUID(0x80000006)
+ */
+
+static inline bool cpuid_amd_hygon_has_l3_cache(struct cpuinfo_x86 *c)
+{
+	return cpuid_leaf(c, 0x80000006)->l3_assoc;
+}
+
 /*
  * CPUID parser exported APIs:
  */
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index a8809778b208..a5d022e15a6b 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -94,7 +94,7 @@ static int amd_cache_northbridges(struct cpuinfo_x86 *c)
 	if (amd_gart_present())
 		amd_northbridges.flags |= AMD_NB_GART;
 
-	if (!cpuid_amd_hygon_has_l3_cache())
+	if (!cpuid_amd_hygon_has_l3_cache(c))
 		return 0;
 
 	/*
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index de8e7125eedd..dc28ffdbdc7f 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -210,7 +210,7 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpuid4_inf
 
 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
 {
-	if (!cpuid_amd_hygon_has_l3_cache())
+	if (!cpuid_amd_hygon_has_l3_cache(c))
 		return;
 
 	if (c->x86 < 0x17) {
@@ -241,7 +241,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
 
 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c)
 {
-	if (!cpuid_amd_hygon_has_l3_cache())
+	if (!cpuid_amd_hygon_has_l3_cache(c))
 		return;
 
 	/*
@@ -257,7 +257,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 
 	ci->num_leaves = boot_cpu_has(X86_FEATURE_TOPOEXT) ?
 		cpuid_subleaf_count(c, 0x8000001d) :
-		cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3;
+		cpuid_amd_hygon_has_l3_cache(c) ? 4 : 3;
 }
 
 void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
-- 
2.49.0

[PATCH v3 43/44] x86/cpu: Rescan CPUID table after PSN disable

[Ahmed S. Darwish]

On Pentium-III and Transmeta CPUs, disabling the CPUID(0x3) Processor
Serial Number (PSN) can affect the maximum valid CPUID standard leaf.

Rescan the CPU's CPUID table in that case, not to have stale cached data.
Use parsed CPUID(0x0) access, instead of direct CPUID query, afterwards.

Rename squash_the_stupid_serial_number() to disable_cpu_serial_number()
and explain the rational for disabling the CPU's PSN.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/common.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 023613698b15..81fe33976ceb 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -327,15 +327,17 @@ bool cpuid_feature(void)
 	return flag_is_changeable_p(X86_EFLAGS_ID);
 }
 
-static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
+/*
+ * For privacy concerns, disable legacy Intel and Transmeta CPUID(0x3)
+ * feature, Processor Serial Number, by default.
+ */
+static void disable_cpu_serial_number(struct cpuinfo_x86 *c)
 {
 	unsigned long lo, hi;
 
 	if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
 		return;
 
-	/* Disable processor serial number: */
-
 	rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 	lo |= 0x200000;
 	wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
@@ -343,8 +345,12 @@ static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 	pr_notice("CPU serial number disabled.\n");
 	clear_cpu_cap(c, X86_FEATURE_PN);
 
-	/* Disabling the serial number may affect the cpuid level */
-	c->cpuid_level = cpuid_eax(0);
+	/*
+	 * Disabling CPUID(0x3) might have affected the maximum standard
+	 * CPUID level.  Rescan the CPU's CPUID table afterwards.
+	 */
+	cpuid_parser_scan_cpu(c);
+	c->cpuid_level = cpuid_leaf(c, 0x0)->max_std_leaf;
 }
 
 static int __init x86_serial_nr_setup(char *s)
@@ -354,7 +360,7 @@ static int __init x86_serial_nr_setup(char *s)
 }
 __setup("serialnumber", x86_serial_nr_setup);
 #else
-static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
+static inline void disable_cpu_serial_number(struct cpuinfo_x86 *c)
 {
 }
 #endif
@@ -1968,7 +1974,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
 	bus_lock_init();
 
 	/* Disable the PN if appropriate */
-	squash_the_stupid_serial_number(c);
+	disable_cpu_serial_number(c);
 
 	/* Set up SMEP/SMAP/UMIP */
 	setup_smep(c);
-- 
2.49.0

[PATCH v3 44/44] x86/cpu: Rescan CPUID table after unlocking full CPUID range

[Ahmed S. Darwish]

Intel CPUs have an MSR bit to limit CPUID enumeration to leaf two, which
can be set by old BIOSen before booting Linux.

Rescan the CPUID table after unlocking the CPU's full CPUID range.  Use
parsed CPUID(0x0) access, instead of a direct CPUID query, afterwards.

References: 066941bd4eeb ("x86: unmask CPUID levels on Intel CPUs")
References: 0c2f6d04619e ("x86/topology/intel: Unlock CPUID before evaluating anything")
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/intel.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 06c249110c8b..fe4d1cf479c2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -192,11 +192,14 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c)
 		return;
 
 	/*
-	 * The BIOS can have limited CPUID to leaf 2, which breaks feature
-	 * enumeration. Unlock it and update the maximum leaf info.
+	 * Intel CPUs have an MSR bit to limit CPUID enumeration to CPUID(0x2),
+	 * which can be set by old BIOSes before booting Linux.  If enabled,
+	 * unlock the CPU's full CPUID range and rescan its CPUID table.
 	 */
-	if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0)
-		c->cpuid_level = cpuid_eax(0);
+	if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
+		cpuid_parser_scan_cpu(c);
+		c->cpuid_level = cpuid_leaf(c, 0x0)->max_std_leaf;
+	}
 }
 
 static void early_init_intel(struct cpuinfo_x86 *c)
-- 
2.49.0

Re: [PATCH v3 41/44] x86/cpu: <asm/processor.h>: Do not include CPUID API header

[kernel test robot]

Hi Ahmed,

kernel test robot noticed the following build errors:

[auto build test ERROR on 19272b37aa4f83ca52bdf9c16d5d81bdd1354494]

url:    https://github.com/intel-lab-lkp/linux/commits/Ahmed-S-Darwish/x86-cpuid-Remove-transitional-asm-cpuid-h-header/20250613-075051
base:   19272b37aa4f83ca52bdf9c16d5d81bdd1354494
patch link:    https://lore.kernel.org/r/20250612234010.572636-42-darwi%40linutronix.de
patch subject: [PATCH v3 41/44] x86/cpu: <asm/processor.h>: Do not include CPUID API header
config: i386-randconfig-004-20250613 (https://download.01.org/0day-ci/archive/20250613/202506132039.imS2Pflx-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250613/202506132039.imS2Pflx-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506132039.imS2Pflx-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/cpufreq/longrun.c: In function 'longrun_get':
>> drivers/cpufreq/longrun.c:143:9: error: implicit declaration of function 'cpuid' [-Werror=implicit-function-declaration]
     143 |         cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
         |         ^~~~~
   cc1: some warnings being treated as errors


vim +/cpuid +143 drivers/cpufreq/longrun.c

^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  135  
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  136  static unsigned int longrun_get(unsigned int cpu)
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  137  {
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  138  	u32 eax, ebx, ecx, edx;
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  139  
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  140  	if (cpu)
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  141  		return 0;
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  142  
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16 @143  	cpuid(0x80860007, &eax, &ebx, &ecx, &edx);
2d06d8c49afdcc arch/x86/kernel/cpu/cpufreq/longrun.c  Dominik Brodowski 2011-03-27  144  	pr_debug("cpuid eax is %u\n", eax);
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  145  
48ee923a666d4c arch/x86/kernel/cpu/cpufreq/longrun.c  Dave Jones        2009-01-17  146  	return eax * 1000;
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  147  }
^1da177e4c3f41 arch/i386/kernel/cpu/cpufreq/longrun.c Linus Torvalds    2005-04-16  148  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 02/44] ASoC: Intel: avs: Include CPUID header at file scope

[Cezary Rojewski]

On 2025-06-13 1:39 AM, Ahmed S. Darwish wrote:
> Commit
> 
>      cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platforms")
> 
> includes the main CPUID header from within a C function.  This obviously
> works by luck and forbids valid refactorings inside the CPUID header.
> 
> Include the CPUID header at file scope instead.
> 
> Note, for the CPUID(0x15) leaf number, use CPUID_LEAF_TSC instead of
> defining a custom local macro for it.


The existing location of #include isn't my best work, clearly. Thank you 
for addressing that, Ahmed. For the avs-driver bits:

Acked-by: Cezary Rojewski <cezary.rojewski@intel.com>

> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
> ---
>   sound/soc/intel/avs/tgl.c | 25 ++++++++++++++++---------
>   1 file changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c
> index 9dbb3ad0954a..cf19d3a7ced2 100644
> --- a/sound/soc/intel/avs/tgl.c
> +++ b/sound/soc/intel/avs/tgl.c
> @@ -10,8 +10,6 @@
>   #include "avs.h"
>   #include "messages.h"
>   
> -#define CPUID_TSC_LEAF 0x15
> -
>   static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
>   {
>   	core_mask &= AVS_MAIN_CORE_MASK;
> @@ -39,22 +37,31 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stal
>   	return avs_dsp_core_stall(adev, core_mask, stall);
>   }
>   
> +#ifdef CONFIG_X86
> +#include <asm/cpuid/api.h>
> +static unsigned int intel_crystal_freq_hz(void)
> +{
> +	return cpuid_ecx(CPUID_LEAF_TSC);
> +}
> +#else
> +static unsigned int intel_crystal_freq_hz(void)
> +{
> +	return 0;
> +}
> +#endif /* !CONFIG_X86 */
> +
>   static int avs_tgl_config_basefw(struct avs_dev *adev)
>   {
> +	unsigned int freq = intel_crystal_freq_hz();
>   	struct pci_dev *pci = adev->base.pci;
>   	struct avs_bus_hwid hwid;
>   	int ret;
> -#ifdef CONFIG_X86
> -	unsigned int ecx;
>   
> -#include <asm/cpuid/api.h>
> -	ecx = cpuid_ecx(CPUID_TSC_LEAF);
> -	if (ecx) {
> -		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx);
> +	if (freq) {
> +		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(freq), &freq);
>   		if (ret)
>   			return AVS_IPC_RET(ret);
>   	}
> -#endif
>   
>   	hwid.device = pci->device;
>   	hwid.subsystem = pci->subsystem_vendor | (pci->subsystem_device << 16);

Re: [PATCH v3 02/44] ASoC: Intel: avs: Include CPUID header at file scope

[Borislav Petkov]

On Fri, Jun 13, 2025 at 01:39:28AM +0200, Ahmed S. Darwish wrote:
> +#ifdef CONFIG_X86
> +#include <asm/cpuid/api.h>
> +static unsigned int intel_crystal_freq_hz(void)
> +{
> +	return cpuid_ecx(CPUID_LEAF_TSC);

I'm guessing this will get eventually converted to the parsed struct in the
end?

I guess I'll have to continue reading and see... :)

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v3 16/44] thermal: intel: Reorder headers alphabetically

[Borislav Petkov]

On Fri, Jun 13, 2025 at 01:39:42AM +0200, Ahmed S. Darwish wrote:
> The source file uses cpuid_*() macros, but it does not include
> <asm/cpuid/api.h>.  Sort its include lines so that the CPUID header can
> be included next.
> 
> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
> ---
>  drivers/thermal/intel/x86_pkg_temp_thermal.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)

Can we merge all those silly includes sorting patches into a single, per-topic
or per-tree patch respectively please?

A single includes sorting patch is fine too since the whole pile will go
through tip eventually.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v3 02/44] ASoC: Intel: avs: Include CPUID header at file scope

[Ahmed S. Darwish]

On Mon, 16 Jun 2025, Cezary Rojewski wrote:
>
> The existing location of #include isn't my best work, clearly. Thank
> you for addressing that, Ahmed. For the avs-driver bits:
>
> Acked-by: Cezary Rojewski <cezary.rojewski@intel.com>
>

Sure, no problem.  Thanks for the Acked-by :-)

Re: [PATCH v3 02/44] ASoC: Intel: avs: Include CPUID header at file scope

[Ahmed S. Darwish]

On Fri, 04 Jul 2025, Borislav Petkov wrote:
>
> I'm guessing this will get eventually converted to the parsed struct in
> the end?
>
> I guess I'll have to continue reading and see... :)
>

Yup, next iteration of this PQ shall also convert all the CPUID(0x15)
call sites, as they're quite simple :)

Re: [PATCH v3 16/44] thermal: intel: Reorder headers alphabetically

[Ahmed S. Darwish]

On Fri, 04 Jul 2025, Borislav Petkov wrote:
>
> Can we merge all those silly includes sorting patches into a single,
> per-topic or per-tree patch respectively please?
>
> A single includes sorting patch is fine too since the whole pile will
> go through tip eventually.
>

Sure, will do.

[PATCH v2 0/6] x86: Disentangle <asm/processor.h> dependency on CPUID headers

[Ahmed S. Darwish]

Hi,

Changelog v2
~~~~~~~~~~~~

Remove all CPUID includes from <asm/processor.h> since only the upcoming
CPUID model needed <asm/processor.h> to include <asm/cpuid/types.h> — not
current mainline code.

Let arch/x86/kvm/reverse_cpuid.h include <asm/cpuid/types.h> since it
references its CPUID_EAX to CPUID_EDX macros.  At this series v1, it
implicitly included the CPUID types header through <asm/cpufeature.h>
through <asm/processor.h>.

Drop the "x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs" patch from
this series.  After a second look, it should be part of the CPUID model
PQ instead.

Changelog v1
~~~~~~~~~~~~

( [PATCH v1 0/7] x86: Disentangle <asm/processor.h> dependency on CPUID APIs
  https://lore.kernel.org/lkml/20250612234010.572636-1-darwi@linutronix.de )
  
This series avoids including the full CPUID API from <asm/processor.h>.
That header only needs the CPUID data types and not the full API.

Let <asm/processor.h> include <asm/cpuid/types.h> instead of
<asm/cpuid/api.h>.

Modify all CPUID call sites which implicitly included the CPUID API
though <asm/processor.h> to explicitly include <asm/cpuid/api.h> instead.

This work prepares for an upcoming v4 of the CPUID model:

    [PATCH v3 00/44] x86: Introduce a centralized CPUID data model
    https://lore.kernel.org/lkml/20250612234010.572636-1-darwi@linutronix.de

where <asm/cpuid/api.h> needs to include <asm/processor.h>, thus creating
a circular dependency if not resolved beforehand…  Patches 1->19 of the
v3 above had parts of this series circular dependency disentanglement.

Per Boris' remarks above, merge the header includes reorderings into two
patches only: one patch for x86 and one for drivers.

The 0-day bot x86-32 compilation error:

    Re: [PATCH v3 41/44] x86/cpu: <asm/processor.h>: Do not include CPUID…
    https://lore.kernel.org/lkml/202506132039.imS2Pflx-lkp@intel.com

is also fixed in this series.

Beside the call sites converted at CPUID model v3 above, this series also
switches below files:

    arch/x86/kernel/cpu/microcode/core.c
    arch/x86/kernel/cpu/microcode/intel.c
    arch/x86/kernel/cpu/mshyperv.c
    drivers/cpufreq/longrun.c
    drivers/cpufreq/powernow-k7.c
    drivers/cpufreq/powernow-k8.c

to explicitly include <asm/cpuid/api.h>.

Based on v6.16-rc5.

Thanks!

8<----

Ahmed S. Darwish (6):
  x86/cpuid: Remove transitional <asm/cpuid.h> header
  ASoC: Intel: avs: Include CPUID header at file scope
  x86: Reorder headers alphabetically
  drivers: Reorder headers alphabetically
  treewide: Explicitly include CPUID headers
  x86/cpu: <asm/processor.h>: Do not include CPUID API header

 arch/x86/boot/compressed/pgtable_64.c        |  1 +
 arch/x86/boot/startup/sme.c                  |  9 +--
 arch/x86/coco/tdx/tdx.c                      |  6 +-
 arch/x86/events/amd/core.c                   |  2 +
 arch/x86/events/amd/ibs.c                    |  1 +
 arch/x86/events/amd/lbr.c                    |  2 +
 arch/x86/events/amd/power.c                  |  3 +
 arch/x86/events/amd/uncore.c                 | 15 ++---
 arch/x86/events/intel/core.c                 |  1 +
 arch/x86/events/intel/lbr.c                  |  1 +
 arch/x86/events/zhaoxin/core.c               | 12 ++--
 arch/x86/include/asm/acrn.h                  |  2 +
 arch/x86/include/asm/cpuid.h                 |  8 ---
 arch/x86/include/asm/microcode.h             |  1 +
 arch/x86/include/asm/processor.h             |  1 -
 arch/x86/include/asm/xen/hypervisor.h        |  1 +
 arch/x86/kernel/cpu/amd.c                    | 26 ++++----
 arch/x86/kernel/cpu/centaur.c                |  1 +
 arch/x86/kernel/cpu/hygon.c                  |  1 +
 arch/x86/kernel/cpu/mce/core.c               | 63 ++++++++++----------
 arch/x86/kernel/cpu/mce/inject.c             |  1 +
 arch/x86/kernel/cpu/microcode/core.c         | 23 +++----
 arch/x86/kernel/cpu/microcode/intel.c        | 12 ++--
 arch/x86/kernel/cpu/mshyperv.c               | 29 +++++----
 arch/x86/kernel/cpu/resctrl/core.c           |  6 +-
 arch/x86/kernel/cpu/resctrl/monitor.c        |  1 +
 arch/x86/kernel/cpu/scattered.c              |  3 +-
 arch/x86/kernel/cpu/sgx/main.c               |  3 +
 arch/x86/kernel/cpu/topology_amd.c           |  1 +
 arch/x86/kernel/cpu/topology_common.c        |  3 +-
 arch/x86/kernel/cpu/topology_ext.c           |  1 +
 arch/x86/kernel/cpu/transmeta.c              |  3 +
 arch/x86/kernel/cpu/zhaoxin.c                |  1 +
 arch/x86/kernel/cpuid.c                      |  1 +
 arch/x86/kernel/paravirt.c                   | 29 ++++-----
 arch/x86/kvm/cpuid.h                         |  3 +
 arch/x86/kvm/mmu/spte.c                      |  1 +
 arch/x86/kvm/reverse_cpuid.h                 |  2 +
 drivers/cpufreq/longrun.c                    |  7 ++-
 drivers/cpufreq/powernow-k7.c                | 14 ++---
 drivers/cpufreq/powernow-k8.c                | 17 +++---
 drivers/cpufreq/speedstep-lib.c              |  6 +-
 drivers/firmware/efi/libstub/x86-5lvl.c      |  1 +
 drivers/hwmon/fam15h_power.c                 | 14 +++--
 drivers/hwmon/k10temp.c                      |  2 +
 drivers/hwmon/k8temp.c                       | 12 ++--
 drivers/thermal/intel/intel_hfi.c            |  1 +
 drivers/thermal/intel/x86_pkg_temp_thermal.c | 15 ++---
 sound/soc/intel/avs/tgl.c                    | 25 +++++---
 49 files changed, 229 insertions(+), 165 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h

base-commit: d7b8f8e20813f0179d8ef519541a3527e7661d3a
-- 
2.49.0

[PATCH v2 1/6] x86/cpuid: Remove transitional <asm/cpuid.h> header

[Ahmed S. Darwish]

All CPUID call sites were updated at commit:

    968e30006807 ("x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header")

to include <asm/cpuid/api.h> instead of <asm/cpuid.h>.

The <asm/cpuid.h> header was still retained as a wrapper, just in case
some new code in -next started using it.  Now that everything is merged
to Linus' tree, remove the header.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid.h | 8 --------
 1 file changed, 8 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h

diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
deleted file mode 100644
index d5749b25fa10..000000000000
--- a/arch/x86/include/asm/cpuid.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_X86_CPUID_H
-#define _ASM_X86_CPUID_H
-
-#include <asm/cpuid/api.h>
-
-#endif /* _ASM_X86_CPUID_H */
-- 
2.49.0

[PATCH v2 2/6] ASoC: Intel: avs: Include CPUID header at file scope

[Ahmed S. Darwish]

Commit

    cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platforms")

includes the main CPUID header from within a C function.  This works by
luck and forbids valid refactorings inside the CPUID header.

Include the CPUID header at file scope instead.

Note, for the CPUID(0x15) leaf number, use CPUID_LEAF_TSC instead of
defining a custom local macro for it.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Acked-by: Cezary Rojewski <cezary.rojewski@intel.com>
---
 sound/soc/intel/avs/tgl.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c
index 9dbb3ad0954a..cf19d3a7ced2 100644
--- a/sound/soc/intel/avs/tgl.c
+++ b/sound/soc/intel/avs/tgl.c
@@ -10,8 +10,6 @@
 #include "avs.h"
 #include "messages.h"
 
-#define CPUID_TSC_LEAF 0x15
-
 static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
 {
 	core_mask &= AVS_MAIN_CORE_MASK;
@@ -39,22 +37,31 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stal
 	return avs_dsp_core_stall(adev, core_mask, stall);
 }
 
+#ifdef CONFIG_X86
+#include <asm/cpuid/api.h>
+static unsigned int intel_crystal_freq_hz(void)
+{
+	return cpuid_ecx(CPUID_LEAF_TSC);
+}
+#else
+static unsigned int intel_crystal_freq_hz(void)
+{
+	return 0;
+}
+#endif /* !CONFIG_X86 */
+
 static int avs_tgl_config_basefw(struct avs_dev *adev)
 {
+	unsigned int freq = intel_crystal_freq_hz();
 	struct pci_dev *pci = adev->base.pci;
 	struct avs_bus_hwid hwid;
 	int ret;
-#ifdef CONFIG_X86
-	unsigned int ecx;
 
-#include <asm/cpuid/api.h>
-	ecx = cpuid_ecx(CPUID_TSC_LEAF);
-	if (ecx) {
-		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx);
+	if (freq) {
+		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(freq), &freq);
 		if (ret)
 			return AVS_IPC_RET(ret);
 	}
-#endif
 
 	hwid.device = pci->device;
 	hwid.subsystem = pci->subsystem_vendor | (pci->subsystem_device << 16);
-- 
2.49.0

[PATCH v2 3/6] x86: Reorder headers alphabetically

[Ahmed S. Darwish]

Multiple x86 source files use the cpuid_*() macros, but implicitly
include the main CPUID API header through <asm/processor.h> instead.

Sort their include lines so that <asm/cpuid/api.h> can be explicitly
included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/startup/sme.c           |  8 ++--
 arch/x86/coco/tdx/tdx.c               |  5 ++-
 arch/x86/events/amd/uncore.c          | 14 +++---
 arch/x86/events/zhaoxin/core.c        | 11 +++--
 arch/x86/kernel/cpu/amd.c             | 25 +++++------
 arch/x86/kernel/cpu/mce/core.c        | 62 +++++++++++++--------------
 arch/x86/kernel/cpu/microcode/core.c  | 22 +++++-----
 arch/x86/kernel/cpu/microcode/intel.c | 11 ++---
 arch/x86/kernel/cpu/mshyperv.c        | 28 ++++++------
 arch/x86/kernel/cpu/resctrl/core.c    |  5 ++-
 arch/x86/kernel/cpu/scattered.c       |  2 +-
 arch/x86/kernel/cpu/topology_common.c |  2 +-
 arch/x86/kernel/paravirt.c            | 28 ++++++------
 13 files changed, 114 insertions(+), 109 deletions(-)

diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c
index 70ea1748c0a7..922b236be02f 100644
--- a/arch/x86/boot/startup/sme.c
+++ b/arch/x86/boot/startup/sme.c
@@ -34,15 +34,15 @@
  */
 #define USE_EARLY_PGTABLE_L5
 
+#include <linux/cc_platform.h>
 #include <linux/kernel.h>
-#include <linux/mm.h>
 #include <linux/mem_encrypt.h>
-#include <linux/cc_platform.h>
+#include <linux/mm.h>
 
+#include <asm/coco.h>
 #include <asm/init.h>
-#include <asm/setup.h>
 #include <asm/sections.h>
-#include <asm/coco.h>
+#include <asm/setup.h>
 #include <asm/sev.h>
 
 #define PGD_FLAGS		_KERNPG_TABLE_NOENC
diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index 7b2833705d47..7bc11836c46a 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -8,16 +8,17 @@
 #include <linux/export.h>
 #include <linux/io.h>
 #include <linux/kexec.h>
+
 #include <asm/coco.h>
-#include <asm/tdx.h>
-#include <asm/vmx.h>
 #include <asm/ia32.h>
 #include <asm/insn.h>
 #include <asm/insn-eval.h>
 #include <asm/paravirt_types.h>
 #include <asm/pgtable.h>
 #include <asm/set_memory.h>
+#include <asm/tdx.h>
 #include <asm/traps.h>
+#include <asm/vmx.h>
 
 /* MMIO direction */
 #define EPT_READ	0
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e8b6af199c73..c1483ef16c0b 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -5,18 +5,18 @@
  * Author: Jacob Shin <jacob.shin@amd.com>
  */
 
-#include <linux/perf_event.h>
-#include <linux/percpu.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/init.h>
 #include <linux/cpu.h>
-#include <linux/cpumask.h>
 #include <linux/cpufeature.h>
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/percpu.h>
+#include <linux/perf_event.h>
+#include <linux/slab.h>
 #include <linux/smp.h>
+#include <linux/types.h>
 
-#include <asm/perf_event.h>
 #include <asm/msr.h>
+#include <asm/perf_event.h>
 
 #define NUM_COUNTERS_NB		4
 #define NUM_COUNTERS_L2		4
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 4bdfcf091200..d59992364880 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -5,16 +5,16 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include <linux/stddef.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/slab.h>
 #include <linux/export.h>
+#include <linux/init.h>
 #include <linux/nmi.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/types.h>
 
+#include <asm/apic.h>
 #include <asm/cpufeature.h>
 #include <asm/hardirq.h>
-#include <asm/apic.h>
 #include <asm/msr.h>
 
 #include "../perf_event.h"
@@ -616,4 +616,3 @@ __init int zhaoxin_pmu_init(void)
 
 	return 0;
 }
-
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 655f44f89ded..6e2ee9ed76d2 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1,32 +1,33 @@
 // SPDX-License-Identifier: GPL-2.0-only
-#include <linux/export.h>
+
 #include <linux/bitops.h>
 #include <linux/elf.h>
-#include <linux/mm.h>
-
+#include <linux/export.h>
 #include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/platform_data/x86/amd-fch.h>
+#include <linux/random.h>
 #include <linux/sched.h>
 #include <linux/sched/clock.h>
-#include <linux/random.h>
 #include <linux/topology.h>
-#include <linux/platform_data/x86/amd-fch.h>
-#include <asm/processor.h>
+
 #include <asm/apic.h>
 #include <asm/cacheinfo.h>
 #include <asm/cpu.h>
 #include <asm/cpu_device_id.h>
-#include <asm/spec-ctrl.h>
-#include <asm/smp.h>
+#include <asm/debugreg.h>
+#include <asm/delay.h>
+#include <asm/msr.h>
 #include <asm/numa.h>
 #include <asm/pci-direct.h>
-#include <asm/delay.h>
-#include <asm/debugreg.h>
+#include <asm/processor.h>
 #include <asm/resctrl.h>
-#include <asm/msr.h>
 #include <asm/sev.h>
+#include <asm/smp.h>
+#include <asm/spec-ctrl.h>
 
 #ifdef CONFIG_X86_64
-# include <asm/mmconfig.h>
+#include <asm/mmconfig.h>
 #endif
 
 #include "cpu.h"
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 4da4eab56c81..5a11c522ea97 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -9,52 +9,52 @@
  * Author: Andi Kleen
  */
 
-#include <linux/thread_info.h>
 #include <linux/capability.h>
-#include <linux/miscdevice.h>
-#include <linux/ratelimit.h>
-#include <linux/rcupdate.h>
-#include <linux/kobject.h>
-#include <linux/uaccess.h>
-#include <linux/kdebug.h>
-#include <linux/kernel.h>
-#include <linux/percpu.h>
-#include <linux/string.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/delay.h>
+#include <linux/cpu.h>
 #include <linux/ctype.h>
-#include <linux/sched.h>
-#include <linux/sysfs.h>
-#include <linux/types.h>
-#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/fs.h>
+#include <linux/hardirq.h>
 #include <linux/init.h>
+#include <linux/irq_work.h>
+#include <linux/kdebug.h>
+#include <linux/kernel.h>
+#include <linux/kexec.h>
 #include <linux/kmod.h>
-#include <linux/poll.h>
+#include <linux/kobject.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
 #include <linux/nmi.h>
-#include <linux/cpu.h>
+#include <linux/percpu.h>
+#include <linux/poll.h>
 #include <linux/ras.h>
-#include <linux/smp.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/debugfs.h>
-#include <linux/irq_work.h>
-#include <linux/export.h>
+#include <linux/ratelimit.h>
+#include <linux/rcupdate.h>
+#include <linux/sched.h>
 #include <linux/set_memory.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/string.h>
 #include <linux/sync_core.h>
+#include <linux/syscore_ops.h>
+#include <linux/sysfs.h>
 #include <linux/task_work.h>
-#include <linux/hardirq.h>
-#include <linux/kexec.h>
+#include <linux/thread_info.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
 
-#include <asm/fred.h>
 #include <asm/cpu_device_id.h>
-#include <asm/processor.h>
-#include <asm/traps.h>
-#include <asm/tlbflush.h>
+#include <asm/fred.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
+#include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/tdx.h>
+#include <asm/tlbflush.h>
+#include <asm/traps.h>
 
 #include "internal.h"
 
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index fe50eb5b7c4a..9243ed3ded85 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -17,27 +17,27 @@
 
 #define pr_fmt(fmt) "microcode: " fmt
 
-#include <linux/platform_device.h>
-#include <linux/stop_machine.h>
-#include <linux/syscore_ops.h>
-#include <linux/miscdevice.h>
 #include <linux/capability.h>
-#include <linux/firmware.h>
+#include <linux/cpu.h>
 #include <linux/cpumask.h>
-#include <linux/kernel.h>
 #include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/cpu.h>
-#include <linux/nmi.h>
+#include <linux/firmware.h>
 #include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/miscdevice.h>
 #include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/nmi.h>
+#include <linux/platform_device.h>
+#include <linux/stop_machine.h>
+#include <linux/syscore_ops.h>
 
 #include <asm/apic.h>
+#include <asm/cmdline.h>
 #include <asm/cpu_device_id.h>
+#include <asm/msr.h>
 #include <asm/perf_event.h>
 #include <asm/processor.h>
-#include <asm/cmdline.h>
-#include <asm/msr.h>
 #include <asm/setup.h>
 
 #include "internal.h"
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 371ca6eac00e..99fda8f7dba7 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -11,21 +11,22 @@
  *		      H Peter Anvin" <hpa@zytor.com>
  */
 #define pr_fmt(fmt) "microcode: " fmt
+
+#include <linux/cpu.h>
 #include <linux/earlycpio.h>
 #include <linux/firmware.h>
-#include <linux/uaccess.h>
 #include <linux/initrd.h>
 #include <linux/kernel.h>
+#include <linux/mm.h>
 #include <linux/slab.h>
-#include <linux/cpu.h>
+#include <linux/uaccess.h>
 #include <linux/uio.h>
-#include <linux/mm.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/msr.h>
 #include <asm/processor.h>
-#include <asm/tlbflush.h>
 #include <asm/setup.h>
-#include <asm/msr.h>
+#include <asm/tlbflush.h>
 
 #include "internal.h"
 
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index c78f860419d6..d0491bba9e30 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -6,33 +6,35 @@
  * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
  */
 
-#include <linux/types.h>
-#include <linux/time.h>
 #include <linux/clocksource.h>
-#include <linux/init.h>
+#include <linux/efi.h>
 #include <linux/export.h>
 #include <linux/hardirq.h>
-#include <linux/efi.h>
+#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kexec.h>
 #include <linux/random.h>
-#include <asm/processor.h>
-#include <asm/hypervisor.h>
+#include <linux/time.h>
+#include <linux/types.h>
+
+#include <clocksource/hyperv_timer.h>
 #include <hyperv/hvhdk.h>
-#include <asm/mshyperv.h>
+
+#include <asm/apic.h>
 #include <asm/desc.h>
+#include <asm/hypervisor.h>
+#include <asm/i8259.h>
 #include <asm/idtentry.h>
 #include <asm/irq_regs.h>
-#include <asm/i8259.h>
-#include <asm/apic.h>
-#include <asm/timer.h>
-#include <asm/reboot.h>
-#include <asm/nmi.h>
-#include <clocksource/hyperv_timer.h>
+#include <asm/mshyperv.h>
 #include <asm/msr.h>
+#include <asm/nmi.h>
 #include <asm/numa.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
 #include <asm/svm.h>
+#include <asm/timer.h>
 
 /* Is Linux running on nested Microsoft Hypervisor */
 bool hv_nested;
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 187d527ef73b..35285567beec 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -17,13 +17,14 @@
 #define pr_fmt(fmt)	"resctrl: " fmt
 
 #include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/err.h>
 #include <linux/cpuhotplug.h>
+#include <linux/err.h>
+#include <linux/slab.h>
 
 #include <asm/cpu_device_id.h>
 #include <asm/msr.h>
 #include <asm/resctrl.h>
+
 #include "internal.h"
 
 /*
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index dbf6d71bdf18..3d23b943f596 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -4,8 +4,8 @@
  */
 #include <linux/cpu.h>
 
-#include <asm/memtype.h>
 #include <asm/apic.h>
+#include <asm/memtype.h>
 #include <asm/processor.h>
 
 #include "cpu.h"
diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index b5a5e1411469..48c47d02d8a9 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -3,8 +3,8 @@
 
 #include <xen/xen.h>
 
-#include <asm/intel-family.h>
 #include <asm/apic.h>
+#include <asm/intel-family.h>
 #include <asm/processor.h>
 #include <asm/smp.h>
 
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index ab3e172dcc69..3d745cd25a43 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -6,34 +6,34 @@
     2007 - x86_64 support added by Glauber de Oliveira Costa, Red Hat Inc
 */
 
+#include <linux/bcd.h>
+#include <linux/efi.h>
 #include <linux/errno.h>
-#include <linux/init.h>
 #include <linux/export.h>
-#include <linux/efi.h>
-#include <linux/bcd.h>
 #include <linux/highmem.h>
+#include <linux/init.h>
 #include <linux/kprobes.h>
 #include <linux/pgtable.h>
 #include <linux/static_call.h>
 
+#include <asm/apic.h>
 #include <asm/bug.h>
-#include <asm/paravirt.h>
 #include <asm/debugreg.h>
+#include <asm/delay.h>
 #include <asm/desc.h>
+#include <asm/fixmap.h>
+#include <asm/gsseg.h>
+#include <asm/io_bitmap.h>
+#include <asm/irq.h>
+#include <asm/msr.h>
+#include <asm/paravirt.h>
+#include <asm/pgalloc.h>
 #include <asm/setup.h>
+#include <asm/special_insns.h>
 #include <asm/time.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/delay.h>
-#include <asm/fixmap.h>
-#include <asm/apic.h>
-#include <asm/tlbflush.h>
 #include <asm/timer.h>
-#include <asm/special_insns.h>
 #include <asm/tlb.h>
-#include <asm/io_bitmap.h>
-#include <asm/gsseg.h>
-#include <asm/msr.h>
+#include <asm/tlbflush.h>
 
 /* stub always returning 0. */
 DEFINE_ASM_FUNC(paravirt_ret0, "xor %eax,%eax", .entry.text);
-- 
2.49.0

[PATCH v2 4/6] drivers: Reorder headers alphabetically

[Ahmed S. Darwish]

Multiple drivers use the cpuid_*() macros, but implicitly include the
main CPUID header through <asm/processor.h> instead.

Sort their include lines so that <asm/cpuid/api.h> can be explicitly
included next.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 drivers/cpufreq/longrun.c                    |  6 +++---
 drivers/cpufreq/powernow-k7.c                | 13 ++++++-------
 drivers/cpufreq/powernow-k8.c                | 16 ++++++++--------
 drivers/cpufreq/speedstep-lib.c              |  5 +++--
 drivers/hwmon/fam15h_power.c                 | 13 +++++++------
 drivers/hwmon/k8temp.c                       | 11 ++++++-----
 drivers/thermal/intel/x86_pkg_temp_thermal.c | 14 +++++++-------
 7 files changed, 40 insertions(+), 38 deletions(-)

diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
index 1caaec7c280b..263c48b8f628 100644
--- a/drivers/cpufreq/longrun.c
+++ b/drivers/cpufreq/longrun.c
@@ -5,15 +5,15 @@
  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  */
 
+#include <linux/cpufreq.h>
+#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
 #include <linux/timex.h>
 
+#include <asm/cpu_device_id.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
-#include <asm/cpu_device_id.h>
 
 static struct cpufreq_driver	longrun_driver;
 
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
index 31039330a3ba..0608040fcd1e 100644
--- a/drivers/cpufreq/powernow-k7.c
+++ b/drivers/cpufreq/powernow-k7.c
@@ -15,20 +15,20 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/cpufreq.h>
+#include <linux/dmi.h>
+#include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
 #include <linux/slab.h>
 #include <linux/string.h>
-#include <linux/dmi.h>
 #include <linux/timex.h>
-#include <linux/io.h>
 
-#include <asm/timer.h>		/* Needed for recalibrate_cpu_khz() */
-#include <asm/msr.h>
 #include <asm/cpu_device_id.h>
+#include <asm/msr.h>
+#include <asm/timer.h>		/* Needed for recalibrate_cpu_khz() */
 
 #ifdef CONFIG_X86_POWERNOW_K7_ACPI
 #include <linux/acpi.h>
@@ -691,4 +691,3 @@ MODULE_LICENSE("GPL");
 
 late_initcall(powernow_init);
 module_exit(powernow_exit);
-
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index f7512b4e923e..2b5cdd8f1c0a 100644
--- a/drivers/cpufreq/powernow-k8.c
+++ b/drivers/cpufreq/powernow-k8.c
@@ -26,22 +26,22 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/acpi.h>
+#include <linux/cpufreq.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
-#include <linux/smp.h>
 #include <linux/module.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
+#include <linux/mutex.h>
 #include <linux/slab.h>
+#include <linux/smp.h>
 #include <linux/string.h>
-#include <linux/cpumask.h>
-#include <linux/io.h>
-#include <linux/delay.h>
 
 #include <asm/msr.h>
 #include <asm/cpu_device_id.h>
 
-#include <linux/acpi.h>
-#include <linux/mutex.h>
 #include <acpi/processor.h>
 
 #define VERSION "version 2.20.00"
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 0b66df4ed513..f08817331aec 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -9,14 +9,15 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/cpufreq.h>
+#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
 
 #include <asm/msr.h>
 #include <asm/tsc.h>
+
 #include "speedstep-lib.h"
 
 #define PFX "speedstep-lib: "
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index 8ecebea53651..5a5674e85f63 100644
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -6,20 +6,21 @@
  * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
  */
 
+#include <linux/bitops.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
 #include <linux/err.h>
-#include <linux/hwmon.h>
 #include <linux/hwmon-sysfs.h>
+#include <linux/hwmon.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/pci.h>
-#include <linux/bitops.h>
-#include <linux/cpu.h>
-#include <linux/cpumask.h>
-#include <linux/time.h>
 #include <linux/sched.h>
+#include <linux/time.h>
 #include <linux/topology.h>
-#include <asm/processor.h>
+
 #include <asm/msr.h>
+#include <asm/processor.h>
 
 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
 MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 2b80ac410cd1..8c1efce9a04b 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -7,13 +7,14 @@
  * Inspired from the w83785 and amd756 drivers.
  */
 
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/pci.h>
-#include <linux/hwmon.h>
 #include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/init.h>
+#include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
 #include <asm/processor.h>
 
 #define TEMP_FROM_REG(val)	(((((val) >> 16) & 0xff) - 49) * 1000)
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index 3fc679b6f11b..c843cb5fc5c3 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -5,19 +5,19 @@
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
-#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/err.h>
 #include <linux/init.h>
 #include <linux/intel_tcc.h>
-#include <linux/err.h>
+#include <linux/module.h>
 #include <linux/param.h>
-#include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/slab.h>
 #include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
 #include <linux/thermal.h>
-#include <linux/debugfs.h>
 
 #include <asm/cpu_device_id.h>
 #include <asm/msr.h>
-- 
2.49.0

[PATCH v2 5/6] treewide: Explicitly include CPUID headers

[Ahmed S. Darwish]

Modify all CPUID call sites which implicitly include any of the CPUID
headers through <asm/processor.h> to explicitly include the CPUID headers
instead.

This allows disentangling <asm/cpuid/api.h> and <asm/cpuid/types.h> from
<asm/processor.h> at a later step.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/compressed/pgtable_64.c        | 1 +
 arch/x86/boot/startup/sme.c                  | 1 +
 arch/x86/coco/tdx/tdx.c                      | 1 +
 arch/x86/events/amd/core.c                   | 2 ++
 arch/x86/events/amd/ibs.c                    | 1 +
 arch/x86/events/amd/lbr.c                    | 2 ++
 arch/x86/events/amd/power.c                  | 3 +++
 arch/x86/events/amd/uncore.c                 | 1 +
 arch/x86/events/intel/core.c                 | 1 +
 arch/x86/events/intel/lbr.c                  | 1 +
 arch/x86/events/zhaoxin/core.c               | 1 +
 arch/x86/include/asm/acrn.h                  | 2 ++
 arch/x86/include/asm/microcode.h             | 1 +
 arch/x86/include/asm/xen/hypervisor.h        | 1 +
 arch/x86/kernel/cpu/amd.c                    | 1 +
 arch/x86/kernel/cpu/centaur.c                | 1 +
 arch/x86/kernel/cpu/hygon.c                  | 1 +
 arch/x86/kernel/cpu/mce/core.c               | 1 +
 arch/x86/kernel/cpu/mce/inject.c             | 1 +
 arch/x86/kernel/cpu/microcode/core.c         | 1 +
 arch/x86/kernel/cpu/microcode/intel.c        | 1 +
 arch/x86/kernel/cpu/mshyperv.c               | 1 +
 arch/x86/kernel/cpu/resctrl/core.c           | 1 +
 arch/x86/kernel/cpu/resctrl/monitor.c        | 1 +
 arch/x86/kernel/cpu/scattered.c              | 1 +
 arch/x86/kernel/cpu/sgx/main.c               | 3 +++
 arch/x86/kernel/cpu/topology_amd.c           | 1 +
 arch/x86/kernel/cpu/topology_common.c        | 1 +
 arch/x86/kernel/cpu/topology_ext.c           | 1 +
 arch/x86/kernel/cpu/transmeta.c              | 3 +++
 arch/x86/kernel/cpu/zhaoxin.c                | 1 +
 arch/x86/kernel/cpuid.c                      | 1 +
 arch/x86/kernel/paravirt.c                   | 1 +
 arch/x86/kvm/cpuid.h                         | 3 +++
 arch/x86/kvm/mmu/spte.c                      | 1 +
 arch/x86/kvm/reverse_cpuid.h                 | 2 ++
 drivers/cpufreq/longrun.c                    | 1 +
 drivers/cpufreq/powernow-k7.c                | 1 +
 drivers/cpufreq/powernow-k8.c                | 1 +
 drivers/cpufreq/speedstep-lib.c              | 1 +
 drivers/firmware/efi/libstub/x86-5lvl.c      | 1 +
 drivers/hwmon/fam15h_power.c                 | 1 +
 drivers/hwmon/k10temp.c                      | 2 ++
 drivers/hwmon/k8temp.c                       | 1 +
 drivers/thermal/intel/intel_hfi.c            | 1 +
 drivers/thermal/intel/x86_pkg_temp_thermal.c | 1 +
 46 files changed, 59 insertions(+)

diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index bdd26050dff7..d94d98595780 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -2,6 +2,7 @@
 #include "misc.h"
 #include <asm/bootparam.h>
 #include <asm/bootparam_utils.h>
+#include <asm/cpuid/api.h>
 #include <asm/e820/types.h>
 #include <asm/processor.h>
 #include "../string.h"
diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c
index 922b236be02f..6a58ab568390 100644
--- a/arch/x86/boot/startup/sme.c
+++ b/arch/x86/boot/startup/sme.c
@@ -40,6 +40,7 @@
 #include <linux/mm.h>
 
 #include <asm/coco.h>
+#include <asm/cpuid/api.h>
 #include <asm/init.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c
index 7bc11836c46a..4ed8ec642646 100644
--- a/arch/x86/coco/tdx/tdx.c
+++ b/arch/x86/coco/tdx/tdx.c
@@ -10,6 +10,7 @@
 #include <linux/kexec.h>
 
 #include <asm/coco.h>
+#include <asm/cpuid/api.h>
 #include <asm/ia32.h>
 #include <asm/insn.h>
 #include <asm/insn-eval.h>
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index b20661b8621d..d28d45ceb707 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -7,8 +7,10 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/jiffies.h>
+
 #include <asm/apicdef.h>
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/nmi.h>
 
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 112f43b23ebf..0c7848e6149e 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -15,6 +15,7 @@
 #include <linux/sched/clock.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "../perf_event.h"
diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
index d24da377df77..5b437dc8e4ce 100644
--- a/arch/x86/events/amd/lbr.c
+++ b/arch/x86/events/amd/lbr.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/perf_event.h>
+
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/perf_event.h>
 
diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c
index dad42790cf7d..744dffa42dee 100644
--- a/arch/x86/events/amd/power.c
+++ b/arch/x86/events/amd/power.c
@@ -10,8 +10,11 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/perf_event.h>
+
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
+
 #include "../perf_event.h"
 
 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index c1483ef16c0b..5261f12007df 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -15,6 +15,7 @@
 #include <linux/smp.h>
 #include <linux/types.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/perf_event.h>
 
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c2fb729c270e..ebbcdf82b494 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -17,6 +17,7 @@
 #include <linux/kvm_host.h>
 
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/hardirq.h>
 #include <asm/intel-family.h>
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 7aa59966e7c3..0d1ec3651735 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -3,6 +3,7 @@
 #include <linux/types.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index d59992364880..15bb9c9c9358 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -14,6 +14,7 @@
 
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/hardirq.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h
index fab11192c60a..db42b477c41d 100644
--- a/arch/x86/include/asm/acrn.h
+++ b/arch/x86/include/asm/acrn.h
@@ -2,6 +2,8 @@
 #ifndef _ASM_X86_ACRN_H
 #define _ASM_X86_ACRN_H
 
+#include <asm/cpuid/api.h>
+
 /*
  * This CPUID returns feature bitmaps in EAX.
  * Guest VM uses this to detect the appropriate feature bit.
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 8b41f26f003b..645e65ac1586 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -3,6 +3,7 @@
 #define _ASM_X86_MICROCODE_H
 
 #include <asm/msr.h>
+#include <asm/cpuid/api.h>
 
 struct cpu_signature {
 	unsigned int sig;
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index c2fc7869b996..7c596cebfb78 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -37,6 +37,7 @@ extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
 
 #include <asm/bug.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 #define XEN_SIGNATURE "XenVMMXenVMM"
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 6e2ee9ed76d2..6bfe714c75dd 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -15,6 +15,7 @@
 #include <asm/cacheinfo.h>
 #include <asm/cpu.h>
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/delay.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index a3b55db35c96..cc5a390dcd07 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -5,6 +5,7 @@
 
 #include <asm/cpu.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/e820/api.h>
 #include <asm/mtrr.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 2154f12766fb..75ad7eb1301a 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -10,6 +10,7 @@
 
 #include <asm/apic.h>
 #include <asm/cpu.h>
+#include <asm/cpuid/api.h>
 #include <asm/smp.h>
 #include <asm/numa.h>
 #include <asm/cacheinfo.h>
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 5a11c522ea97..31ff1c578b40 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -47,6 +47,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/fred.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index d02c4f556cd0..42c82c14c48a 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -26,6 +26,7 @@
 
 #include <asm/amd/nb.h>
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/irq_vectors.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 9243ed3ded85..eae9eaa455ba 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -35,6 +35,7 @@
 #include <asm/apic.h>
 #include <asm/cmdline.h>
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/perf_event.h>
 #include <asm/processor.h>
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 99fda8f7dba7..30d20f78f07d 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -23,6 +23,7 @@
 #include <linux/uio.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 #include <asm/setup.h>
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index d0491bba9e30..771a65e6fefb 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -22,6 +22,7 @@
 #include <hyperv/hvhdk.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/desc.h>
 #include <asm/hypervisor.h>
 #include <asm/i8259.h>
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 35285567beec..52d3753ab020 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/resctrl.h>
 
diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c
index c261558276cd..5dffb9453d77 100644
--- a/arch/x86/kernel/cpu/resctrl/monitor.c
+++ b/arch/x86/kernel/cpu/resctrl/monitor.c
@@ -21,6 +21,7 @@
 #include <linux/resctrl.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "internal.h"
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 3d23b943f596..15f8752d4132 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -5,6 +5,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/processor.h>
 
diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c
index 2de01b379aa3..00bf42f4c536 100644
--- a/arch/x86/kernel/cpu/sgx/main.c
+++ b/arch/x86/kernel/cpu/sgx/main.c
@@ -14,8 +14,11 @@
 #include <linux/slab.h>
 #include <linux/sysfs.h>
 #include <linux/vmalloc.h>
+
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/sgx.h>
+
 #include "driver.h"
 #include "encl.h"
 #include "encls.h"
diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index 843b1655ab45..abc6f5a7a486 100644
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -2,6 +2,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index 48c47d02d8a9..38189e4fea0e 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -4,6 +4,7 @@
 #include <xen/xen.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/intel-family.h>
 #include <asm/processor.h>
 #include <asm/smp.h>
diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topology_ext.c
index 467b0326bf1a..eb915c73895f 100644
--- a/arch/x86/kernel/cpu/topology_ext.c
+++ b/arch/x86/kernel/cpu/topology_ext.c
@@ -2,6 +2,7 @@
 #include <linux/cpu.h>
 
 #include <asm/apic.h>
+#include <asm/cpuid/api.h>
 #include <asm/memtype.h>
 #include <asm/processor.h>
 
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index 42c939827621..1fdcd69c625c 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -3,8 +3,11 @@
 #include <linux/sched.h>
 #include <linux/sched/clock.h>
 #include <linux/mm.h>
+
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
+
 #include "cpu.h"
 
 static void early_init_transmeta(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 89b1c8a70fe8..cfcfb6221e3f 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -4,6 +4,7 @@
 
 #include <asm/cpu.h>
 #include <asm/cpufeature.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "cpu.h"
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index dae436253de4..cbd04b677fd1 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -37,6 +37,7 @@
 #include <linux/gfp.h>
 #include <linux/completion.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 3d745cd25a43..b7fc3b78086c 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -18,6 +18,7 @@
 
 #include <asm/apic.h>
 #include <asm/bug.h>
+#include <asm/cpuid/api.h>
 #include <asm/debugreg.h>
 #include <asm/delay.h>
 #include <asm/desc.h>
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index d3f5ae15a7ca..89f8ed3fb37a 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -3,8 +3,11 @@
 #define ARCH_X86_KVM_CPUID_H
 
 #include "reverse_cpuid.h"
+
 #include <asm/cpu.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
+
 #include <uapi/asm/kvm_para.h>
 
 extern u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly;
diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
index cfce03d8f123..e7b69275ae50 100644
--- a/arch/x86/kvm/mmu/spte.c
+++ b/arch/x86/kvm/mmu/spte.c
@@ -15,6 +15,7 @@
 #include "x86.h"
 #include "spte.h"
 
+#include <asm/cpuid/api.h>
 #include <asm/e820/api.h>
 #include <asm/memtype.h>
 #include <asm/vmx.h>
diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h
index fde0ae986003..be774dcf5e97 100644
--- a/arch/x86/kvm/reverse_cpuid.h
+++ b/arch/x86/kvm/reverse_cpuid.h
@@ -3,8 +3,10 @@
 #define ARCH_X86_KVM_REVERSE_CPUID_H
 
 #include <uapi/asm/kvm.h>
+
 #include <asm/cpufeature.h>
 #include <asm/cpufeatures.h>
+#include <asm/cpuid/types.h>
 
 /*
  * Define a KVM-only feature flag.
diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c
index 263c48b8f628..3429857feb96 100644
--- a/drivers/cpufreq/longrun.c
+++ b/drivers/cpufreq/longrun.c
@@ -12,6 +12,7 @@
 #include <linux/timex.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
index 0608040fcd1e..7a324a829a43 100644
--- a/drivers/cpufreq/powernow-k7.c
+++ b/drivers/cpufreq/powernow-k7.c
@@ -27,6 +27,7 @@
 #include <linux/timex.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/timer.h>		/* Needed for recalibrate_cpu_khz() */
 
diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c
index 2b5cdd8f1c0a..e909eee30edd 100644
--- a/drivers/cpufreq/powernow-k8.c
+++ b/drivers/cpufreq/powernow-k8.c
@@ -41,6 +41,7 @@
 
 #include <asm/msr.h>
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 
 #include <acpi/processor.h>
 
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index f08817331aec..3c323cd8eede 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/tsc.h>
 
diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
index f1c5fb45d5f7..029ad80cf0b4 100644
--- a/drivers/firmware/efi/libstub/x86-5lvl.c
+++ b/drivers/firmware/efi/libstub/x86-5lvl.c
@@ -2,6 +2,7 @@
 #include <linux/efi.h>
 
 #include <asm/boot.h>
+#include <asm/cpuid/api.h>
 #include <asm/desc.h>
 #include <asm/efi.h>
 
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index 5a5674e85f63..1ecaef25f04e 100644
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -19,6 +19,7 @@
 #include <linux/time.h>
 #include <linux/topology.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/processor.h>
 
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index babf2413d666..12115654689a 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -20,7 +20,9 @@
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/pci_ids.h>
+
 #include <asm/amd/node.h>
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 8c1efce9a04b..eb167be245b9 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -15,6 +15,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/processor.h>
 
 #define TEMP_FROM_REG(val)	(((((val) >> 16) & 0xff) - 49) * 1000)
diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c
index bd2fca7dc017..c910cc563d9d 100644
--- a/drivers/thermal/intel/intel_hfi.c
+++ b/drivers/thermal/intel/intel_hfi.c
@@ -41,6 +41,7 @@
 #include <linux/topology.h>
 #include <linux/workqueue.h>
 
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "intel_hfi.h"
diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c
index c843cb5fc5c3..1b9e0b49856c 100644
--- a/drivers/thermal/intel/x86_pkg_temp_thermal.c
+++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c
@@ -20,6 +20,7 @@
 #include <linux/thermal.h>
 
 #include <asm/cpu_device_id.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 
 #include "thermal_interrupt.h"
-- 
2.49.0

[PATCH v2 6/6] x86/cpu: <asm/processor.h>: Do not include CPUID API header

[Ahmed S. Darwish]

<asm/processor.h> includes the CPUID API header <asm/cpuid/api.h> but it
does not need it.

Remove the CPUID API header include.

This allows the CPUID API header to include <asm/processor.h> without
introducing a circular dependency, which is needed for the upcoming CPUID
model and parser.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/processor.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index bde58f6510ac..910e36b0c00d 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -16,7 +16,6 @@ struct vm86;
 #include <uapi/asm/sigcontext.h>
 #include <asm/current.h>
 #include <asm/cpufeatures.h>
-#include <asm/cpuid/api.h>
 #include <asm/page.h>
 #include <asm/pgtable_types.h>
 #include <asm/percpu.h>
-- 
2.49.0

Re: [PATCH v2 0/6] x86: Disentangle <asm/processor.h> dependency on CPUID headers

[Ahmed S. Darwish]

On Wed, 09 Jul 2025, Ahmed S. Darwish wrote:
>
> Changelog v2
> ~~~~~~~~~~~~
>

Sorry, not my best day.  This was meant as a reply to another PQ.

Kindly ignore this and check instead:

    [PATCH v2 0/6] x86: Disentangle <asm/processor.h> dependency on CPUID headers
    https://lore.kernel.org/lkml/20250709203033.90125-1-darwi@linutronix.de

Thanks,

--
Ahmed S. Darwish
Linutronix GmbH