From: Peter Zijlstra <peterz@infradead.org>
To: "Xin Li (Intel)" <xin@zytor.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com,
seanjc@google.com, pbonzini@redhat.com, brgerst@gmail.com,
tony.luck@intel.com, fenghuay@nvidia.com
Subject: Re: [PATCH v1 2/3] x86/traps: Initialize DR7 by writing its architectural reset value
Date: Fri, 13 Jun 2025 09:15:36 +0200 [thread overview]
Message-ID: <20250613071536.GG2273038@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20250613070118.3694407-3-xin@zytor.com>
On Fri, Jun 13, 2025 at 12:01:16AM -0700, Xin Li (Intel) wrote:
> While at it, replace the hardcoded debug register number 7 with the
> existing DR_CONTROL macro for clarity.
Yeah, not really a fan of that... IMO that obfuscates the code more than
it helps, consider:
> - get_debugreg(dr7, 7);
> + get_debugreg(dr7, DR_CONTROL);
and:
> - for (i = 0; i < 8; i++) {
> - /* Ignore db4, db5 */
> - if ((i == 4) || (i == 5))
> - continue;
> + /* Control register first */
> + set_debugreg(DR7_RESET_VALUE, DR_CONTROL);
> + set_debugreg(0, DR_STATUS);
>
> + /* Ignore db4, db5 */
> + for (i = DR_FIRSTADDR; i <= DR_LASTADDR; i++)
I had to git-grep DR_{FIRST,LAST}ADDR to double check this was correct :(
Also, you now write them in the order:
dr7, dr6, /* dr4, dr5 */, dr0, dr1, dr2, dr3
My OCD disagrees with this :-)
next prev parent reply other threads:[~2025-06-13 7:20 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 7:01 [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Xin Li (Intel)
2025-06-13 7:01 ` [PATCH v1 1/3] x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h> Xin Li (Intel)
2025-06-13 14:18 ` Sean Christopherson
2025-06-13 17:58 ` Xin Li
2025-06-13 20:03 ` Sean Christopherson
2025-06-13 21:38 ` Xin Li
2025-06-13 7:01 ` [PATCH v1 2/3] x86/traps: Initialize DR7 by writing its architectural reset value Xin Li (Intel)
2025-06-13 7:15 ` Peter Zijlstra [this message]
2025-06-13 7:51 ` Xin Li
2025-06-13 7:59 ` H. Peter Anvin
2025-06-13 8:16 ` Peter Zijlstra
2025-06-13 14:10 ` Sean Christopherson
2025-06-13 17:36 ` Xin Li
2025-06-13 7:01 ` [PATCH v1 3/3] x86/traps: Initialize DR6 " Xin Li (Intel)
2025-06-13 7:18 ` [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Peter Zijlstra
2025-06-13 7:37 ` Xin Li
2025-06-13 22:43 ` Sohil Mehta
2025-06-13 23:22 ` Xin Li
2025-06-14 3:38 ` H. Peter Anvin
2025-06-16 8:15 ` Ethan Zhao
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