From: Peter Zijlstra <peterz@infradead.org>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Xin Li <xin@zytor.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, x86@kernel.org, seanjc@google.com,
pbonzini@redhat.com, brgerst@gmail.com, tony.luck@intel.com,
fenghuay@nvidia.com
Subject: Re: [PATCH v1 2/3] x86/traps: Initialize DR7 by writing its architectural reset value
Date: Fri, 13 Jun 2025 10:16:10 +0200 [thread overview]
Message-ID: <20250613081610.GK2273038@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <310B2567-8680-4E1D-B1BB-A56809466ED4@zytor.com>
On Fri, Jun 13, 2025 at 12:59:04AM -0700, H. Peter Anvin wrote:
> Incidentally, do you know the following x86 register sequences in the proper order?
>
> ax, cx, dx, bx, sp, bp, si, di, ...
Yes, I get annoyed at that every time I decode regs :-)
> al, cl, dl, bl, ah, ch, dh, bh
> es, cs, ss, ds, fs, gs
These I don't know from the top of my head -- I've not had to use them enough.
next prev parent reply other threads:[~2025-06-13 8:17 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 7:01 [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Xin Li (Intel)
2025-06-13 7:01 ` [PATCH v1 1/3] x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h> Xin Li (Intel)
2025-06-13 14:18 ` Sean Christopherson
2025-06-13 17:58 ` Xin Li
2025-06-13 20:03 ` Sean Christopherson
2025-06-13 21:38 ` Xin Li
2025-06-13 7:01 ` [PATCH v1 2/3] x86/traps: Initialize DR7 by writing its architectural reset value Xin Li (Intel)
2025-06-13 7:15 ` Peter Zijlstra
2025-06-13 7:51 ` Xin Li
2025-06-13 7:59 ` H. Peter Anvin
2025-06-13 8:16 ` Peter Zijlstra [this message]
2025-06-13 14:10 ` Sean Christopherson
2025-06-13 17:36 ` Xin Li
2025-06-13 7:01 ` [PATCH v1 3/3] x86/traps: Initialize DR6 " Xin Li (Intel)
2025-06-13 7:18 ` [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Peter Zijlstra
2025-06-13 7:37 ` Xin Li
2025-06-13 22:43 ` Sohil Mehta
2025-06-13 23:22 ` Xin Li
2025-06-14 3:38 ` H. Peter Anvin
2025-06-16 8:15 ` Ethan Zhao
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