From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, tglx@linutronix.de,
dave.hansen@linux.intel.com, irogers@google.com,
adrian.hunter@intel.com, jolsa@kernel.org,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org
Cc: dapeng1.mi@linux.intel.com, ak@linux.intel.com,
zide.chen@intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [RFC PATCH 12/12] perf/x86/intel: Support extended registers
Date: Fri, 13 Jun 2025 06:49:43 -0700 [thread overview]
Message-ID: <20250613134943.3186517-13-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20250613134943.3186517-1-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Support YMM, APX, OPMASK, ZMM, and SSP if there is XSAVES support.
Disable large PEBS if the extended regs are required.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5706ee562684..4218067b1843 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4035,6 +4035,8 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
flags &= ~PERF_SAMPLE_REGS_USER;
if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
+ if (event_has_extended_regs2(event))
+ flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
return flags;
}
@@ -5295,6 +5297,26 @@ static void intel_extended_regs_init(struct pmu *pmu)
x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_XMM);
x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
+
+ if (boot_cpu_has(X86_FEATURE_AVX) &&
+ cpu_has_xfeatures(XFEATURE_MASK_YMM, NULL))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_YMM);
+ if (boot_cpu_has(X86_FEATURE_APX) &&
+ cpu_has_xfeatures(XFEATURE_MASK_APX, NULL))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_APX);
+ if (boot_cpu_has(X86_FEATURE_AVX512F)) {
+ if (cpu_has_xfeatures(XFEATURE_MASK_OPMASK, NULL))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_OPMASK);
+ if (cpu_has_xfeatures(XFEATURE_MASK_ZMM_Hi256, NULL))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_ZMMH);
+ if (cpu_has_xfeatures(XFEATURE_MASK_Hi16_ZMM, NULL))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_H16ZMM);
+ }
+ if (cpu_feature_enabled(X86_FEATURE_USER_SHSTK))
+ x86_pmu.ext_regs_mask |= BIT_ULL(X86_EXT_REGS_CET);
+
+ if (x86_pmu.ext_regs_mask != BIT_ULL(X86_EXT_REGS_XMM))
+ x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS2;
}
static void update_pmu_cap(struct pmu *pmu)
--
2.38.1
next prev parent reply other threads:[~2025-06-13 13:50 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 13:49 [RFC PATCH 00/12] Support vector and more extended registers in perf kan.liang
2025-06-13 13:49 ` [RFC PATCH 01/12] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-13 13:49 ` [RFC PATCH 02/12] perf/x86: Setup the regs data kan.liang
2025-06-13 13:49 ` [RFC PATCH 03/12] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-06-13 14:39 ` Dave Hansen
2025-06-13 14:54 ` Liang, Kan
2025-06-13 15:19 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 04/12] perf: Move has_extended_regs() to header file kan.liang
2025-06-13 13:49 ` [RFC PATCH 05/12] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-13 15:15 ` Dave Hansen
2025-06-13 17:51 ` Liang, Kan
2025-06-13 15:34 ` Dave Hansen
2025-06-13 18:14 ` Liang, Kan
2025-06-13 13:49 ` [RFC PATCH 06/12] perf: Support extension of sample_regs kan.liang
2025-06-17 8:00 ` Mi, Dapeng
2025-06-17 8:14 ` Peter Zijlstra
2025-06-17 9:49 ` Mi, Dapeng
2025-06-17 10:28 ` Peter Zijlstra
2025-06-17 12:14 ` Mi, Dapeng
2025-06-17 13:33 ` Peter Zijlstra
2025-06-17 14:06 ` Peter Zijlstra
2025-06-17 14:24 ` Mark Rutland
2025-06-17 14:44 ` Peter Zijlstra
2025-06-17 14:55 ` Mark Rutland
2025-06-17 19:00 ` Mark Brown
2025-06-17 20:32 ` Liang, Kan
2025-06-18 9:35 ` Peter Zijlstra
2025-06-18 10:10 ` Liang, Kan
2025-06-18 13:30 ` Peter Zijlstra
2025-06-18 13:52 ` Liang, Kan
2025-06-18 14:30 ` Dave Hansen
2025-06-18 14:47 ` Dave Hansen
2025-06-18 15:24 ` Liang, Kan
2025-06-18 14:45 ` Peter Zijlstra
2025-06-18 15:22 ` Liang, Kan
2025-06-13 13:49 ` [RFC PATCH 07/12] perf/x86: Add YMMH in extended regs kan.liang
2025-06-13 15:48 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 08/12] perf/x86: Add APX " kan.liang
2025-06-13 16:02 ` Dave Hansen
2025-06-13 17:17 ` Liang, Kan
2025-06-17 8:19 ` Peter Zijlstra
2025-06-13 13:49 ` [RFC PATCH 09/12] perf/x86: Add OPMASK " kan.liang
2025-06-13 13:49 ` [RFC PATCH 10/12] perf/x86: Add ZMM " kan.liang
2025-06-13 13:49 ` [RFC PATCH 11/12] perf/x86: Add SSP " kan.liang
2025-06-13 13:49 ` kan.liang [this message]
2025-06-17 7:50 ` [RFC PATCH 00/12] Support vector and more extended registers in perf Mi, Dapeng
2025-06-17 8:24 ` Peter Zijlstra
2025-06-17 13:52 ` Liang, Kan
2025-06-17 14:29 ` Peter Zijlstra
2025-06-17 15:23 ` Liang, Kan
2025-06-17 17:34 ` Peter Zijlstra
2025-06-18 0:57 ` Mi, Dapeng
2025-06-18 10:47 ` Liang, Kan
2025-06-18 12:28 ` Mi, Dapeng
2025-06-18 13:15 ` Liang, Kan
2025-06-19 0:41 ` Mi, Dapeng
2025-06-19 11:11 ` Liang, Kan
2025-06-19 12:26 ` Mi, Dapeng
2025-06-19 13:38 ` Peter Zijlstra
2025-06-19 14:27 ` Liang, Kan
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