Re: [PATCH 1/4] spi: spi-fsl-dspi: Clear completion counter before initiating transfer

Vladimir Oltean
2025-06-10T11:34:29Z

On Mon, Jun 09, 2025 at 04:32:38PM +0100, James Clark wrote:
> In target mode, extra interrupts can be received between the end of a
> transfer and halting the module if the host continues sending more data.

Presumably you mean not just any extra interrupts can be received, but
specifically CMDTCF, since that triggers the complete(&dspi->xfer_done)
call. Other interrupt sources are masked in XSPI mode and should be
irrelevant.

> If the interrupt from this occurs after the reinit_completion() then the
> completion counter is left at a non-zero value. The next unrelated
> transfer initiated by userspace will then complete immediately without
> waiting for the interrupt or writing to the RX buffer.
>
> Fix it by resetting the counter before the transfer so that lingering
> values are cleared. This is done after clearing the FIFOs and the
> status register but before the transfer is initiated, so no interrupts
> should be received at this point resulting in other race conditions.

Sorry, I don't have a lot of experience with the target mode, and when I
introduced the XSPI FIFO mode, I didn't take target mode into consideration.

The question is, does the module support XSPI FIFO writes in target
mode? In the LS1028A reference manual, I see PUSHR_SLAVE has the upper
16 bits (for the command) hidden, specifically there is no CTAS field
there that would point to one of the CTARE0/CTARE1 registers.
Cross-checking with the S32G3 RM, I see nothing fundamentally different.

I am surprised, given this fact, that the CMDTCF interrupt would fire at
all in target mode.

>
> Fixes: 4f5ee75ea171 ("spi: spi-fsl-dspi: Replace interruptible wait queue with a simple completion")

To be clear, if you ran 'git bisect' to track down this issue, it
wouldn't have pointed you to this commit, would it?