[PATCH 0/3] Add EPSS L3 provider support on QCS8300 SoC

[PATCH 0/3] Add EPSS L3 provider support on QCS8300 SoC

[Raviteja Laggyshetty]

Add Epoch subsystem (EPSS) L3 scaling support on QCS8300 SoC.

Raviteja Laggyshetty (3):
  dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
  interconnect: qcom: Add EPSS L3 support on QCS8300 SoC
  arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node

 .../bindings/interconnect/qcom,osm-l3.yaml      |  1 +
 arch/arm64/boot/dts/qcom/qcs8300.dtsi           | 17 +++++++++++++++++
 drivers/interconnect/qcom/osm-l3.c              |  1 +
 3 files changed, 19 insertions(+)

-- 
2.43.0

[PATCH 1/3] dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC

[Raviteja Laggyshetty]

Add Epoch Subsystem (EPSS) L3 interconnect provider binding for
QCS8300 SoC.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index cd4bb912e0dc..64ad3898abb6 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -35,6 +35,7 @@ properties:
               - qcom,sm8250-epss-l3
               - qcom,sm8350-epss-l3
               - qcom,sm8650-epss-l3
+              - qcom,qcs8300-epss-l3
           - const: qcom,epss-l3
 
   reg:
-- 
2.43.0

[PATCH 2/3] interconnect: qcom: Add EPSS L3 support on QCS8300 SoC

[Raviteja Laggyshetty]

Add Epoch Subsystem (EPSS) L3 interconnect provider support on
QCS8300 SoC.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 drivers/interconnect/qcom/osm-l3.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index baecbf2533f7..d8f1e0a4617b 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -270,6 +270,7 @@ static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
 	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
+	{ .compatible = "qcom,qcs8300-epss-l3", .data = &epss_l3_perf_state },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
-- 
2.43.0

[PATCH 3/3] arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node

[Raviteja Laggyshetty]

Add Epoch Subsystem (EPSS) L3 interconnect provider node for QCS8300 SoC.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 7ada029c32c1..e056b3af21d5 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/firmware/qcom,scm.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -5433,6 +5434,14 @@ rpmhpd_opp_turbo_l1: opp-9 {
 			};
 		};
 
+		epss_l3_cl0: interconnect@18590000 {
+			compatible = "qcom,qcs8300-epss-l3", "qcom,epss-l3";
+				reg = <0x0 0x18590000 0x0 0x1000>;
+				clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+				clock-names = "xo", "alternate";
+				#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss";
 			reg = <0x0 0x18591000 0x0 0x1000>,
@@ -5455,6 +5464,14 @@ cpufreq_hw: cpufreq@18591000 {
 			#freq-domain-cells = <1>;
 		};
 
+		epss_l3_cl1: interconnect@18592000 {
+			compatible = "qcom,qcs8300-epss-l3", "qcom,epss-l3";
+				reg = <0x0 0x18592000 0x0 0x1000>;
+				clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+				clock-names = "xo", "alternate";
+				#interconnect-cells = <1>;
+		};
+
 		remoteproc_gpdsp: remoteproc@20c00000 {
 			compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
 			reg = <0x0 0x20c00000 0x0 0x10000>;
-- 
2.43.0

Re: [PATCH 1/3] dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC

[Krzysztof Kozlowski]

On 17/06/2025 11:06, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding for
> QCS8300 SoC.
> 
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index cd4bb912e0dc..64ad3898abb6 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -35,6 +35,7 @@ properties:
>                - qcom,sm8250-epss-l3
>                - qcom,sm8350-epss-l3
>                - qcom,sm8650-epss-l3
> +              - qcom,qcs8300-epss-l3

Keep order, don't just stuff to the end of the lists.

Isn't this already on your internal checklist/guide?



Best regards,
Krzysztof

Re: [PATCH 2/3] interconnect: qcom: Add EPSS L3 support on QCS8300 SoC

[Krzysztof Kozlowski]

On 17/06/2025 11:06, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
> QCS8300 SoC.
> 
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
>  drivers/interconnect/qcom/osm-l3.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index baecbf2533f7..d8f1e0a4617b 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -270,6 +270,7 @@ static const struct of_device_id osm_l3_of_match[] = {
>  	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
>  	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
>  	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
> +	{ .compatible = "qcom,qcs8300-epss-l3", .data = &epss_l3_perf_state },
Heh, the same as some time ago. We discussed this.

No, stop adding more redundant entries. For explanation look at previous
discussions.

Best regards,
Krzysztof

Re: [PATCH 2/3] interconnect: qcom: Add EPSS L3 support on QCS8300 SoC

[Krzysztof Kozlowski]

On 17/06/2025 11:26, Krzysztof Kozlowski wrote:
> On 17/06/2025 11:06, Raviteja Laggyshetty wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
>> QCS8300 SoC.
>>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> ---
>>  drivers/interconnect/qcom/osm-l3.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
>> index baecbf2533f7..d8f1e0a4617b 100644
>> --- a/drivers/interconnect/qcom/osm-l3.c
>> +++ b/drivers/interconnect/qcom/osm-l3.c
>> @@ -270,6 +270,7 @@ static const struct of_device_id osm_l3_of_match[] = {
>>  	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
>>  	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
>>  	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
>> +	{ .compatible = "qcom,qcs8300-epss-l3", .data = &epss_l3_perf_state },
> Heh, the same as some time ago. We discussed this.
> 
> No, stop adding more redundant entries. For explanation look at previous
> discussions.
> 
You already received exactly the same comments.

https://lore.kernel.org/all/51653aac-76e0-4da2-aea8-16d62b570155@kernel.org/


Best regards,
Krzysztof

Re: [PATCH 2/3] interconnect: qcom: Add EPSS L3 support on QCS8300 SoC

[Raviteja Laggyshetty]

On 6/17/2025 2:56 PM, Krzysztof Kozlowski wrote:
> On 17/06/2025 11:06, Raviteja Laggyshetty wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider support on
>> QCS8300 SoC.
>>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
>> ---
>>  drivers/interconnect/qcom/osm-l3.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
>> index baecbf2533f7..d8f1e0a4617b 100644
>> --- a/drivers/interconnect/qcom/osm-l3.c
>> +++ b/drivers/interconnect/qcom/osm-l3.c
>> @@ -270,6 +270,7 @@ static const struct of_device_id osm_l3_of_match[] = {
>>  	{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
>>  	{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
>>  	{ .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
>> +	{ .compatible = "qcom,qcs8300-epss-l3", .data = &epss_l3_perf_state },
> Heh, the same as some time ago. We discussed this.
>
> No, stop adding more redundant entries. For explanation look at previous
> discussions.

Will remove the compatible "qcom,qcs8300-epss-l3" from driver and retain
it in bindings and devicetree. 

This will allow the driver to probe using generic compatible, without
the need of additional target specific compatible.

>
> Best regards,
> Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node

[Konrad Dybcio]

On 6/17/25 11:06 AM, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node for QCS8300 SoC.
> 
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 7ada029c32c1..e056b3af21d5 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -12,6 +12,7 @@
>  #include <dt-bindings/dma/qcom-gpi.h>
>  #include <dt-bindings/firmware/qcom,scm.h>
>  #include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
>  #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> @@ -5433,6 +5434,14 @@ rpmhpd_opp_turbo_l1: opp-9 {
>  			};
>  		};
>  
> +		epss_l3_cl0: interconnect@18590000 {
> +			compatible = "qcom,qcs8300-epss-l3", "qcom,epss-l3";
> +				reg = <0x0 0x18590000 0x0 0x1000>;
> +				clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +				clock-names = "xo", "alternate";

Very odd indentation

You should also immediately bind these providers to something,
otherwise sync_state will happily take them to whatever minimum
rate the hardware allows, making things worse

Konrad