[PATCH v2 0/4] Add initial support for RZ/N2H SoC and EVK

[PATCH v2 0/4] Add initial support for RZ/N2H SoC and EVK

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds initial support for the Renesas RZ/N2H SoC and
the RZ/N2H Evaluation Board (EVK). The series includes:
1. An initial SoC DTSI for the RZ/N2H SoC, which includes the basic
   configuration of the SoC blocks such as EXT CLKs, 4X CA55, SCIF,
   CPG, GIC, and ARMv8 Timer.
2. A new DTSI for the R9A09G087M44 variant of the RZ/N2H SoC, which
   features a 4-core configuration.
3. Refactoring of the RZ/T2H EVK device tree to extract common entries
   into a new file, `rzt2h-n2h-evk-common.dtsi`, to reduce
   duplication between the RZ/T2H and RZ/N2H EVK device trees.
4. An initial device tree for the RZ/N2H EVK, which includes
   the common entries from the previous step and sets up the board
   model and compatible strings.

Note,
- I've split up this patch from original series [1] to make it easier
  to review and apply.
- This patch series applied on top of the series [2].

[1] https://lore.kernel.org/all/20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://lore.kernel.org/all/20250617162810.154332-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

v1->v2:
- Reordered the `l3_ca55` node and renamed it to `L3_CA55` for consistency
- Renamed the file to `rzt2h-n2h-evk-common.dtsi` to better reflect its
  purpose.
- Updated model string to "Renesas RZ/N2H EVK Board based on r9a09g087m44"
- Added reviewed-by tag from Geert

Cheers,
Prabhakar

Lad Prabhakar (1):
  arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

Paul Barker (3):
  arm64: dts: renesas: Refactor RZ/T2H EVK device tree
  arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC
  arm64: dts: renesas: Add initial support for RZ/N2H EVK

 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  17 +--
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    | 124 ++++++++++++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  16 +++
 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi |  13 ++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     |  24 ++++
 6 files changed, 180 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

-- 
2.49.0

[PATCH v2 1/4] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
the list of blocks added:
- EXT CLKs
- 4X CA55
- SCIF
- CPG
- GIC
- ARMv8 Timer

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
- Reordered the `l3_ca55` node and renamed it to `L3_CA55` for consistency
- Added reviewed-by tag from Geert
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 124 +++++++++++++++++++++
 1 file changed, 124 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
new file mode 100644
index 000000000000..e57a91adcb68
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g087";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sci0: serial@80005000 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80005000 0 0x400>;
+			interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@80280000 {
+			compatible = "renesas,r9a09g087-cpg-mssr";
+			reg = <0 0x80280000 0 0x1000>,
+			      <0 0x81280000 0 0x9000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		gic: interrupt-controller@83000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x83000000 0 0x40000>,
+			      <0x0 0x83040000 0 0x160000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
-- 
2.49.0

[PATCH v2 2/4] arm64: dts: renesas: Refactor RZ/T2H EVK device tree

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so
much overlap between these parts, common device tree entries are moved
to the new file rzt2h-evk-common.dtsi.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- Renamed the file to `rzt2h-n2h-evk-common.dtsi` to better reflect its
  purpose.
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 17 +------------
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 752d4c9f2cae..486584fefead 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -8,24 +8,9 @@
 /dts-v1/;
 
 #include "r9a09g077m44.dtsi"
+#include "rzt2h-n2h-evk-common.dtsi"
 
 / {
 	model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
 	compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
-
-	aliases {
-		serial0 = &sci0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&extal_clk {
-	clock-frequency = <25000000>;
-};
-
-&sci0 {
-	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
new file mode 100644
index 000000000000..5f17996bcd6b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Common Device Tree Source for the RZ/T2H and RZ/N2H EVK boards.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/ {
+	aliases {
+		serial0 = &sci0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&extal_clk {
+	clock-frequency = <25000000>;
+};
+
+&sci0 {
+	status = "okay";
+};
-- 
2.49.0

[PATCH v2 3/4] arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

Add the device tree source include file for the R9A09G087M44 variant of the
Renesas RZ/N2H SoC, which features a 4-core configuration.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
- Added reviewed-by tag from Geert
---
 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
new file mode 100644
index 000000000000..ef0343b53309
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H 4-core SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g087.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g087m44", "renesas,r9a09g087";
+};
-- 
2.49.0

[PATCH v2 4/4] arm64: dts: renesas: Add initial support for RZ/N2H EVK

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

Add an initial devicetree file for the Renesas RZ/N2H Evaluation Board
(EVK).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2:
- Updated model string to "Renesas RZ/N2H EVK Board based on r9a09g087m44"
- Added reviewed-by tag from Geert
---
 arch/arm64/boot/dts/renesas/Makefile             |  2 ++
 .../boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts  | 16 ++++++++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 52d0488cfee3..2bd5d179f757 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -167,5 +167,7 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb
+
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
new file mode 100644
index 000000000000..d6ba14a26f03
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g087m44.dtsi"
+#include "rzt2h-n2h-evk-common.dtsi"
+
+/ {
+	model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
+	compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+};
-- 
2.49.0

Re: [PATCH v2 2/4] arm64: dts: renesas: Refactor RZ/T2H EVK device tree

[Geert Uytterhoeven]

On Tue, 17 Jun 2025 at 19:20, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
>
> The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so
> much overlap between these parts, common device tree entries are moved
> to the new file rzt2h-evk-common.dtsi.
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> - Renamed the file to `rzt2h-n2h-evk-common.dtsi` to better reflect its
>   purpose.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 0/4] Add initial support for RZ/N2H SoC and EVK

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 17 Jun 2025 at 19:20, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> This patch series adds initial support for the Renesas RZ/N2H SoC and
> the RZ/N2H Evaluation Board (EVK). The series includes:
> 1. An initial SoC DTSI for the RZ/N2H SoC, which includes the basic
>    configuration of the SoC blocks such as EXT CLKs, 4X CA55, SCIF,
>    CPG, GIC, and ARMv8 Timer.
> 2. A new DTSI for the R9A09G087M44 variant of the RZ/N2H SoC, which
>    features a 4-core configuration.
> 3. Refactoring of the RZ/T2H EVK device tree to extract common entries
>    into a new file, `rzt2h-n2h-evk-common.dtsi`, to reduce
>    duplication between the RZ/T2H and RZ/N2H EVK device trees.
> 4. An initial device tree for the RZ/N2H EVK, which includes
>    the common entries from the previous step and sets up the board
>    model and compatible strings.
>
> Note,
> - I've split up this patch from original series [1] to make it easier
>   to review and apply.
> - This patch series applied on top of the series [2].
>
> [1] https://lore.kernel.org/all/20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [2] https://lore.kernel.org/all/20250617162810.154332-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> v1->v2:
> - Reordered the `l3_ca55` node and renamed it to `L3_CA55` for consistency
> - Renamed the file to `rzt2h-n2h-evk-common.dtsi` to better reflect its
>   purpose.
> - Updated model string to "Renesas RZ/N2H EVK Board based on r9a09g087m44"
> - Added reviewed-by tag from Geert

Thank you, both [2] and this series are good to go, once the
updated renesas,rsci DT bindings are accepted.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds