From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v6 20/28] KVM: arm64: Support userspace access to streaming mode Z and P registers
Date: Wed, 25 Jun 2025 11:48:11 +0100 [thread overview]
Message-ID: <20250625-kvm-arm64-sme-v6-20-114cff4ffe04@kernel.org> (raw)
In-Reply-To: <20250625-kvm-arm64-sme-v6-0-114cff4ffe04@kernel.org>
SME introduces a mode called streaming mode where the Z, P and optionally
FFR registers can be accessed using the SVE instructions but with the SME
vector length. Reflect this in the ABI for accessing the guest registers by
making the vector length for the vcpu reflect the vector length that would
be seen by the guest were it running, using the SME vector length when the
guest is configured for streaming mode.
Since SME may be present without SVE we also update the existing checks for
access to the Z, P and V registers to check for either SVE or streaming
mode. When not in streaming mode the guest floating point state may be
accessed via the V registers.
Any VMM that supports SME must be aware of the need to configure streaming
mode prior to writing the floating point registers that this creates.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/kvm/guest.c | 38 ++++++++++++++++++++++++++++++++++----
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index 6460bb21e01d..4ba0afa369d5 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -73,6 +73,11 @@ static u64 core_reg_offset_from_id(u64 id)
return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
}
+static bool vcpu_has_sve_regs(const struct kvm_vcpu *vcpu)
+{
+ return vcpu_has_sve(vcpu) || vcpu_in_streaming_mode(vcpu);
+}
+
static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
{
int size;
@@ -110,9 +115,10 @@ static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
/*
* The KVM_REG_ARM64_SVE regs must be used instead of
* KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
- * SVE-enabled vcpus:
+ * SVE-enabled vcpus or when a SME enabled vcpu is in
+ * streaming mode:
*/
- if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
+ if (vcpu_has_sve_regs(vcpu) && core_reg_offset_is_vreg(off))
return -EINVAL;
return size;
@@ -426,6 +432,24 @@ struct vec_state_reg_region {
unsigned int upad; /* extra trailing padding in user memory */
};
+/*
+ * We represent the Z and P registers to userspace using either the
+ * SVE or SME vector length, depending on which features the guest has
+ * and if the guest is in streaming mode.
+ */
+static unsigned int vcpu_sve_cur_vq(struct kvm_vcpu *vcpu)
+{
+ unsigned int vq = 0;
+
+ if (vcpu_has_sve(vcpu))
+ vq = vcpu_sve_max_vq(vcpu);
+
+ if (vcpu_in_streaming_mode(vcpu))
+ vq = vcpu_sme_max_vq(vcpu);
+
+ return vq;
+}
+
/*
* Validate SVE register ID and get sanitised bounds for user/kernel SVE
* register copy
@@ -466,7 +490,7 @@ static int sve_reg_to_region(struct vec_state_reg_region *region,
if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
return -ENOENT;
- vq = vcpu_sve_max_vq(vcpu);
+ vq = vcpu_sve_cur_vq(vcpu);
reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
SVE_SIG_REGS_OFFSET;
@@ -476,7 +500,7 @@ static int sve_reg_to_region(struct vec_state_reg_region *region,
if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
return -ENOENT;
- vq = vcpu_sve_max_vq(vcpu);
+ vq = vcpu_sve_cur_vq(vcpu);
reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
SVE_SIG_REGS_OFFSET;
@@ -515,6 +539,9 @@ static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
if (!kvm_arm_vcpu_vec_finalized(vcpu))
return -EPERM;
+ if (!vcpu_has_sve_regs(vcpu))
+ return -EBUSY;
+
if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
region.klen) ||
clear_user(uptr + region.klen, region.upad))
@@ -541,6 +568,9 @@ static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
if (!kvm_arm_vcpu_vec_finalized(vcpu))
return -EPERM;
+ if (!vcpu_has_sve_regs(vcpu))
+ return -EBUSY;
+
if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
region.klen))
return -EFAULT;
--
2.39.5
next prev parent reply other threads:[~2025-06-25 11:26 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-25 10:47 [PATCH v6 00/28] KVM: arm64: Implement support for SME Mark Brown
2025-06-25 10:47 ` [PATCH v6 01/28] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2025-06-25 10:47 ` [PATCH v6 02/28] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2025-06-25 10:47 ` [PATCH v6 03/28] arm64/fpsimd: Check enable bit for FA64 when saving EFI state Mark Brown
2025-06-25 10:47 ` [PATCH v6 04/28] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2025-06-25 10:47 ` [PATCH v6 05/28] KVM: arm64: Introduce non-UNDEF FGT control Mark Brown
2025-06-25 10:47 ` [PATCH v6 06/28] KVM: arm64: Pay attention to FFR parameter in SVE save and load Mark Brown
2025-06-25 10:47 ` [PATCH v6 07/28] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2025-06-25 10:47 ` [PATCH v6 08/28] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2025-06-25 10:48 ` [PATCH v6 09/28] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2025-06-25 10:48 ` [PATCH v6 10/28] KVM: arm64: Document the KVM ABI for SME Mark Brown
2025-06-25 10:48 ` [PATCH v6 11/28] KVM: arm64: Define internal features " Mark Brown
2025-06-25 10:48 ` [PATCH v6 12/28] KVM: arm64: Rename sve_state_reg_region Mark Brown
2025-06-25 10:48 ` [PATCH v6 13/28] KVM: arm64: Store vector lengths in an array Mark Brown
2025-06-25 10:48 ` [PATCH v6 14/28] KVM: arm64: Implement SME vector length configuration Mark Brown
2025-06-25 10:48 ` [PATCH v6 15/28] KVM: arm64: Support SME control registers Mark Brown
2025-06-25 10:48 ` [PATCH v6 16/28] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2025-06-25 10:48 ` [PATCH v6 17/28] KVM: arm64: Support SME identification registers for guests Mark Brown
2025-06-29 10:08 ` Marc Zyngier
2025-06-25 10:48 ` [PATCH v6 18/28] KVM: arm64: Support SME priority registers Mark Brown
2025-06-29 9:32 ` Marc Zyngier
2025-07-03 18:03 ` Mark Brown
2025-06-25 10:48 ` [PATCH v6 19/28] KVM: arm64: Provide assembly for SME register access Mark Brown
2025-06-25 10:48 ` Mark Brown [this message]
2025-06-25 10:48 ` [PATCH v6 21/28] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2025-06-25 10:48 ` [PATCH v6 22/28] KVM: arm64: Expose SME specific state to userspace Mark Brown
2025-06-25 10:48 ` [PATCH v6 23/28] KVM: arm64: Context switch SME state for guests Mark Brown
2025-06-25 10:48 ` [PATCH v6 24/28] KVM: arm64: Handle SME exceptions Mark Brown
2025-06-25 10:48 ` [PATCH v6 25/28] KVM: arm64: Expose SME to nested guests Mark Brown
2025-06-25 10:48 ` [PATCH v6 26/28] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2025-06-25 10:48 ` [PATCH v6 27/28] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2025-06-25 10:48 ` [PATCH v6 28/28] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
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