[PATCH v4 0/2] Add support for clock controllers and CPU scaling for QCS615

[PATCH v4 0/2] Add support for clock controllers and CPU scaling for QCS615

[Taniya Das]

Add the video, camera, display and gpu clock controller nodes and the
cpufreq-hw node to support cpu scaling.

Clock Dependency:
https://lore.kernel.org/lkml/20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com

Changes in v4:
- Fix the typo(removal of "") from cpufreq-hw node
- Link to v3: https://lore.kernel.org/r/20250612-qcs615-mm-cpu-dt-v3-v3-0-721d5db70342@quicinc.com

Changes in v3:
- Move the cpufreq-hw node under /soc {}
- Add the RB-tag on (v2) from [Konrad]

Changes in v2:
- pad address field to 8 digits [Dmitry]
- Replace cpu/CPU in commit [Dmitry]
- Update the binding to use SC7180 compatible, as QCS615 uses the same
  hardware version.
- Link to v1: https://lore.kernel.org/r/20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Taniya Das (2):
      arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
      arm64: dts: qcom: qcs615: Add CPU scaling clock node

 arch/arm64/boot/dts/qcom/qcs615.dtsi | 80 ++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
---
base-commit: 2ae2aaafb21454f4781c30734959cf223ab486ef
change-id: 20250625-qcs615-mm-cpu-dt-v4-b6b9bc7d3e56
prerequisite-message-id: <20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com>
prerequisite-patch-id: 932a0fe6ddfcc9720eea7e2b29e1bd6ed21fbfca
prerequisite-patch-id: 6414e91724ba90fe820c3d2bb5caa720c99cf3be
prerequisite-patch-id: e4e24f3dc507891b70936c9587ee1416f1a53e6f
prerequisite-patch-id: 23062409b23977940c958bf22a215ae5dc45e93a
prerequisite-patch-id: c35335d37fdf9a7f665f1c6d79d34b091d45e291
prerequisite-patch-id: 9a0caaaa8d25634dd0db5edffbc939eb7e734c6c
prerequisite-patch-id: 66386f8e3c0b0594dad7794f8ff04e6eea2ffb5d
prerequisite-patch-id: 2327271def3656283d53dadb2ce9f8cd561249d1
prerequisite-patch-id: c97840c551e081b0b9bf6c0e77b551935454f62d
prerequisite-patch-id: 71f0eb0fb98c3177dcbe6736c120cba4efef0c33

Best regards,
-- 
Taniya Das <quic_tdas@quicinc.com>

[PATCH v4 1/2] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock

[Taniya Das]

Add support for video, camera, display and gpu clock controller nodes
for QCS615 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3,7 +3,11 @@
  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,qcs615-camcc.h>
+#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs615-videocc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
@@ -1506,6 +1510,18 @@ data-pins {
 			};
 		};
 
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,qcs615-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GPLL0>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		stm@6002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x06002000 0x0 0x1000>,
@@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		videocc: clock-controller@ab00000 {
+			compatible = "qcom,qcs615-videocc";
+			reg = <0 0x0ab00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ad00000 {
+			compatible = "qcom,qcs615-camcc";
+			reg = <0 0x0ad00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,qcs615-dispcc";
+			reg = <0 0x0af00000 0 0x20000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,qcs615-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,

-- 
2.34.1

[PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Taniya Das]

Add cpufreq-hw node to support CPU frequency scaling.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 5adf409d7ce7226042c759cc83ceca331097ae37..d06fc1c157454f635389ff0645fcf4b378270dbc 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -36,6 +36,8 @@ cpu0: cpu@0 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_0>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 
 			l2_0: l2-cache {
@@ -56,6 +58,8 @@ cpu1: cpu@100 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_100>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_100: l2-cache {
 			      compatible = "cache";
@@ -75,6 +79,8 @@ cpu2: cpu@200 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_200>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_200: l2-cache {
 			      compatible = "cache";
@@ -94,6 +100,8 @@ cpu3: cpu@300 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_300>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_300: l2-cache {
 			      compatible = "cache";
@@ -113,6 +121,8 @@ cpu4: cpu@400 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_400>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_400: l2-cache {
 			      compatible = "cache";
@@ -132,6 +142,8 @@ cpu5: cpu@500 {
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			next-level-cache = <&l2_500>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_500: l2-cache {
 			      compatible = "cache";
@@ -151,6 +163,8 @@ cpu6: cpu@600 {
 			capacity-dmips-mhz = <1740>;
 			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_600>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 
 			l2_600: l2-cache {
@@ -171,6 +185,8 @@ cpu7: cpu@700 {
 			capacity-dmips-mhz = <1740>;
 			dynamic-power-coefficient = <404>;
 			next-level-cache = <&l2_700>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 
 			l2_700: l2-cache {
 			      compatible = "cache";
@@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
 				qcom,remote-pid = <2>;
 			};
 		};
+
+		cpufreq_hw: cpufreq@18323000 {
+			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
+			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
+			reg-names = "freq-domain0", "freq-domain1";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
 	};
 
 	arch_timer: timer {

-- 
2.34.1

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Dmitry Baryshkov]

On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support CPU frequency scaling.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>  				qcom,remote-pid = <2>;
>  			};
>  		};
> +
> +		cpufreq_hw: cpufreq@18323000 {
> +			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";

Why? Other platforms use a true SoC as the first entry.

> +			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
> +			reg-names = "freq-domain0", "freq-domain1";
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> +			clock-names = "xo", "alternate";
> +
> +			#freq-domain-cells = <1>;
> +			#clock-cells = <1>;
> +		};
> +
>  	};
>  
>  	arch_timer: timer {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Taniya Das]

On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>> Add cpufreq-hw node to support CPU frequency scaling.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>  				qcom,remote-pid = <2>;
>>  			};
>>  		};
>> +
>> +		cpufreq_hw: cpufreq@18323000 {
>> +			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
> 
> Why? Other platforms use a true SoC as the first entry.
> 
Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
and that was the reason to use the same.

>> +			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
>> +			reg-names = "freq-domain0", "freq-domain1";
>> +
>> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>> +			clock-names = "xo", "alternate";
>> +
>> +			#freq-domain-cells = <1>;
>> +			#clock-cells = <1>;
>> +		};
>> +
>>  	};
>>  
>>  	arch_timer: timer {
>>
>> -- 
>> 2.34.1
>>
> 

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Konrad Dybcio]

On 6/27/25 5:52 AM, Taniya Das wrote:
> 
> 
> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>>  1 file changed, 29 insertions(+)
>>>
>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>  				qcom,remote-pid = <2>;
>>>  			};
>>>  		};
>>> +
>>> +		cpufreq_hw: cpufreq@18323000 {
>>> +			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>
>> Why? Other platforms use a true SoC as the first entry.
>>
> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
> and that was the reason to use the same.

The only compatible consumed by the driver is the last one in this case,
meaning sc7180 is only there so that if we discover quirks very specific
to sc7180 down the line, we can add some exceptions in code

Reusing sc7180 would remove the ability to address any quirks that would
concern qcs615 specifically, which can happen due to hw design, fw
quirks etc.

Konrad

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Dmitry Baryshkov]

On 27/06/2025 06:52, Taniya Das wrote:
> 
> 
> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>>   1 file changed, 29 insertions(+)
>>>
>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>   				qcom,remote-pid = <2>;
>>>   			};
>>>   		};
>>> +
>>> +		cpufreq_hw: cpufreq@18323000 {
>>> +			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>
>> Why? Other platforms use a true SoC as the first entry.
>>
> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
> and that was the reason to use the same.

Please look around. A quick `git grep` would show that every SoC uses 
SoC-specific compatible (although some of them are definitely 
compatible). The reason is pretty simple: each platform might have 
SoC-specific tunings and quirks.

-- 
With best wishes
Dmitry

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Taniya Das]

On 6/27/2025 5:37 PM, Konrad Dybcio wrote:
> On 6/27/25 5:52 AM, Taniya Das wrote:
>>
>>
>> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>>>  1 file changed, 29 insertions(+)
>>>>
>>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>>  				qcom,remote-pid = <2>;
>>>>  			};
>>>>  		};
>>>> +
>>>> +		cpufreq_hw: cpufreq@18323000 {
>>>> +			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>>
>>> Why? Other platforms use a true SoC as the first entry.
>>>
>> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
>> and that was the reason to use the same.
> 
> The only compatible consumed by the driver is the last one in this case,
> meaning sc7180 is only there so that if we discover quirks very specific
> to sc7180 down the line, we can add some exceptions in code
> 
> Reusing sc7180 would remove the ability to address any quirks that would
> concern qcs615 specifically, which can happen due to hw design, fw
> quirks etc.
> 

There are no quirks for QCS615 as the block is a re-use in design. I
will add the new update to use the "qcom,qcs615-cpufreq-hw".

> Konrad

Re: [PATCH v4 2/2] arm64: dts: qcom: qcs615: Add CPU scaling clock node

[Taniya Das]

On 6/27/2025 6:05 PM, Dmitry Baryshkov wrote:
> On 27/06/2025 06:52, Taniya Das wrote:
>>
>>
>> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 ++++++++++++++++++++++++
>>>> +++++
>>>>   1 file changed, 29 insertions(+)
>>>>
>>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>>                   qcom,remote-pid = <2>;
>>>>               };
>>>>           };
>>>> +
>>>> +        cpufreq_hw: cpufreq@18323000 {
>>>> +            compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>>
>>> Why? Other platforms use a true SoC as the first entry.
>>>
>> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
>> and that was the reason to use the same.
> 
> Please look around. A quick `git grep` would show that every SoC uses
> SoC-specific compatible (although some of them are definitely
> compatible). The reason is pretty simple: each platform might have SoC-
> specific tunings and quirks.
> 

Sure Dmitry, I will update to use "qcom,qcs615-cpufreq-hw"