From: Terry Bowman <terry.bowman@amd.com>
To: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<dan.j.williams@intel.com>, <bhelgaas@google.com>,
<shiju.jose@huawei.com>, <ming.li@zohomail.com>,
<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,
<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,
<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<terry.bowman@amd.com>, <linux-cxl@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: [PATCH v10 01/17] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions
Date: Thu, 26 Jun 2025 17:42:36 -0500 [thread overview]
Message-ID: <20250626224252.1415009-2-terry.bowman@amd.com> (raw)
In-Reply-To: <20250626224252.1415009-1-terry.bowman@amd.com>
The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras()
are unnecessary helper functions used only for Endpoints. Remove these
functions as they are not common for all CXL devices and do not provide
value for EP handling.
Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras()
to cxl_handle_cor_ras().
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
drivers/cxl/core/pci.c | 26 ++++++++------------------
1 file changed, 8 insertions(+), 18 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index b50551601c2e..06464a25d8bd 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -664,8 +664,8 @@ void read_cdat_data(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");
-static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
- void __iomem *ras_base)
+static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
void __iomem *addr;
u32 status;
@@ -681,11 +681,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
}
}
-static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
-{
- return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
-}
-
/* CXL spec rev3.0 8.2.4.16.1 */
static void header_log_copy(void __iomem *ras_base, u32 *log)
{
@@ -707,8 +702,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
* Log the state of the RAS status registers and prepare them to log the
* next error status. Return 1 if reset needed.
*/
-static bool __cxl_handle_ras(struct cxl_dev_state *cxlds,
- void __iomem *ras_base)
+static bool cxl_handle_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
u32 hl[CXL_HEADERLOG_SIZE_U32];
void __iomem *addr;
@@ -741,11 +736,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds,
return true;
}
-static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
-{
- return __cxl_handle_ras(cxlds, cxlds->regs.ras);
-}
-
#ifdef CONFIG_PCIEAER_CXL
static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
@@ -824,13 +814,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
struct cxl_dport *dport)
{
- return __cxl_handle_cor_ras(cxlds, dport->regs.ras);
+ return cxl_handle_cor_ras(cxlds, dport->regs.ras);
}
static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
struct cxl_dport *dport)
{
- return __cxl_handle_ras(cxlds, dport->regs.ras);
+ return cxl_handle_ras(cxlds, dport->regs.ras);
}
/*
@@ -927,7 +917,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev)
if (cxlds->rcd)
cxl_handle_rdport_errors(cxlds);
- cxl_handle_endpoint_cor_ras(cxlds);
+ cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
}
}
EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
@@ -956,7 +946,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
* chance the situation is recoverable dump the status of the RAS
* capability registers and bounce the active state of the memdev.
*/
- ue = cxl_handle_endpoint_ras(cxlds);
+ ue = cxl_handle_ras(cxlds, cxlds->regs.ras);
}
--
2.34.1
next prev parent reply other threads:[~2025-06-26 22:43 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 22:42 [PATCH v10 00/17] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-06-26 22:42 ` Terry Bowman [this message]
2025-07-18 17:55 ` [PATCH v10 01/17] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Dave Jiang
2025-07-23 21:58 ` dan.j.williams
2025-07-23 22:15 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 02/17] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-07-23 22:30 ` dan.j.williams
2025-08-09 10:56 ` Alejandro Lucero Palau
2025-08-11 19:14 ` Bowman, Terry
2025-08-11 23:14 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 03/17] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-06-26 23:25 ` Sathyanarayanan Kuppuswamy
2025-06-27 9:53 ` Jonathan Cameron
2025-07-02 16:00 ` Bowman, Terry
2025-06-27 11:32 ` Shiju Jose
2025-07-01 21:27 ` Dave Jiang
2025-07-23 22:56 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 04/17] CXL/AER: Introduce CXL specific AER driver file Terry Bowman
2025-06-26 23:42 ` Sathyanarayanan Kuppuswamy
2025-06-27 10:12 ` Jonathan Cameron
2025-06-27 14:29 ` Bowman, Terry
2025-07-24 0:01 ` dan.j.williams
2025-07-24 17:06 ` Bowman, Terry
2025-07-24 20:32 ` dan.j.williams
2025-07-24 1:16 ` dan.j.williams
2025-07-24 17:02 ` Bowman, Terry
2025-07-24 20:23 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 05/17] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-27 10:24 ` Jonathan Cameron
2025-07-02 16:21 ` Bowman, Terry
2025-07-02 19:54 ` Dan Carpenter
2025-07-02 19:57 ` Bowman, Terry
2025-07-03 10:06 ` Jonathan Cameron
2025-07-01 21:53 ` Dave Jiang
2025-07-02 17:10 ` Bowman, Terry
2025-07-24 2:01 ` dan.j.williams
2025-07-24 17:21 ` Bowman, Terry
2025-07-24 20:55 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 06/17] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-27 11:00 ` Jonathan Cameron
2025-07-02 17:51 ` Bowman, Terry
2025-07-01 23:04 ` Dave Jiang
2025-07-02 17:56 ` Bowman, Terry
2025-07-03 10:11 ` Jonathan Cameron
2025-07-25 0:38 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 07/17] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-27 11:05 ` Jonathan Cameron
2025-07-02 21:06 ` Bowman, Terry
2025-06-27 12:27 ` Shiju Jose
2025-07-02 21:34 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 08/17] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-27 11:12 ` Jonathan Cameron
2025-07-18 18:01 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 09/17] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-27 11:17 ` Jonathan Cameron
2025-07-02 21:41 ` Bowman, Terry
2025-07-18 21:28 ` Dave Jiang
2025-07-18 21:55 ` Bowman, Terry
2025-07-18 22:01 ` Dave Jiang
2025-07-18 22:40 ` Bowman, Terry
2025-07-18 22:45 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 10/17] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-26 22:42 ` [PATCH v10 11/17] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-07-21 21:56 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 12/17] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-27 12:22 ` Shiju Jose
2025-07-02 1:18 ` Alison Schofield
2025-07-02 22:07 ` Bowman, Terry
2025-07-02 21:56 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 13/17] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-27 11:48 ` Jonathan Cameron
2025-07-21 22:17 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 14/17] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-27 11:52 ` Jonathan Cameron
2025-06-27 12:27 ` Shiju Jose
2025-07-21 22:35 ` Dave Jiang
2025-07-22 18:23 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 15/17] CXL/PCI: Introduce CXL Port " Terry Bowman
2025-06-26 22:42 ` [PATCH v10 16/17] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-26 22:42 ` [PATCH v10 17/17] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-07-23 21:55 ` [PATCH v10 00/17] Enable CXL PCIe Port Protocol Error handling and logging dan.j.williams
2025-08-18 15:18 ` Joshua Hahn
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