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Sat, 28 Jun 2025 07:32:50 -0700 (PDT) Received: from localhost.localdomain ([192.34.165.40]) by smtp.gmail.com with ESMTPSA id 00721157ae682-71515bee257sm8393477b3.23.2025.06.28.07.32.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jun 2025 07:32:50 -0700 (PDT) From: John Clark To: heiko@sntech.de Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, John Clark Subject: [PATCH v5 0/2] Add FriendlyElec NanoPi M5 support for Rockchip RK3576 Date: Sat, 28 Jun 2025 10:32:27 -0400 Message-Id: <20250628143229.74460-1-inindev@gmail.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds device tree support for the FriendlyElec NanoPi M5 board, powered by the Rockchip RK3576 SoC (4x Cortex-A72, 4x Cortex-A53, Mali-G52 MC3 GPU, 6 TOPS NPU). The patches enable basic booting and connectivity, including dual 1Gbps Ethernet, USB 3.2, microSD, M.2 PCIe NVMe, and HDMI. Changes in v5: - Addressed Jonas Karlman's feedback: - Added mmc0 alias for SD card - Updated regulator names to match schematic (e.g., vcc12v_dcin, vcc5v0_sys_s5, vcc3v3_m2_keym, vcc3v3_sd_s0, usb3_port2_5v, vcc5v0_usb_otg0, vcc5v_hdmi_tx) - Fixed vcc3v3_sd_s0 voltage to 3.3V - Removed unnecessary regulator-state-mem for fixed regulators - Removed vcc_5v0_device regulator - Added pinctrl for Ethernet PHY reset GPIOs in mdio0 and mdio1 - Used correct pinctrl format for sdmmc and sfc1 (<&pin>) - Increased SPI flash frequency to 50 MHz - Updated LED colors (sys: red, led1/led2: green) and functions (LED_FUNCTION_HEARTBEAT, LED_FUNCTION_LAN) - Dropped rng node (enabled by default) - Omitted HDMI mode-switching GPIO (to be added later with driver support) - Updated pinctrl names to match schematic (e.g., pcie0_pwren_h, sdmmc0_pwren_h, usb3_host_pwren_h, usb_otg0_pwren_h, hp_det_l, pcie0_perstn) Changes in v4: - Addressed Diederik's feedback: - Renamed pinctrl nodes to align with schematic labels - Moved pinctrl-0 and pinctrl-names into button-user sub-node Changes in v3: - Improved (even more) fspi1m1_pins comment for clarity, specifying gpio1_d5, gpio1_c4-c7 (clk, d0-d4) for SPI NOR flash. - Removed redundant #address-cells and #size-cells from sfc1 node, as they are inherited from rk3576.dtsi. Changes in v2: - Fixed DT schema warnings (Rob Herring): - Renamed spi-nor@0 to flash@0 - Renamed pmic@23 pinctrl nodes to end with -pins - Renamed hym8563@51 to rtc@51 and removed clock-frequency - Renamed button@1 to button-user - Addressed Heiko Stuebner's feedback: - Sorted non-addressed nodes alphabetically - Added blank lines in regulator nodes - Improved fspi1m1_pins comment to clarify SPI NOR flash pinmux - Moved status property in saradc to last Patch 1: Updates DT bindings in rockchip.yaml Patch 2: Adds NanoPi M5 device tree and Makefile entry No MAINTAINERS update needed, as the new file is covered by the existing ARM/Rockchip SoC entry. Tested on NanoPi M5 with successful boot and feature validation. Signed-off-by: John Clark --- John Clark (2): dt-bindings: arm: rockchip: add FriendlyElec NanoPi M5 board arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support .../devicetree/bindings/arm/rockchip.yaml | 6 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3576-nanopi-m5.dts | 941 ++++++++++++++++++ 3 files changed, 948 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts -- 2.39.5