From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A16A32F85E0 for ; Fri, 4 Jul 2025 12:59:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751633971; cv=none; b=q6INpuBfmPZBr3aPzXP8dkGlEowZXGxjjUgvXZ6rMdkwYZhkfij3WI+gGnAz510REaPRs4atgmnvRPmIounTk7QnrWsCVQohH20epkxf0jUeng7La1u2/shbQLOc7BwCviFAaOSPxXCJZME3Rrbnsg0yOOr6rCuRYhdaklgmTcQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751633971; c=relaxed/simple; bh=hJbpv5dGff69Y1YddG8Sv73fXBldHYiyvQ0eXRWQ7X4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r1mCQF7aS/erPVvAQnmJAzVKbM4gM5BMBaCwNKgk3KPDi8zOdI9b/cnWhrqvEa7UrQnlP+TnVETg5mqp0RWJS1ngcbEPvJJVs54II+thbc9vZVbAwoLKC9arYsaa6JADKPcR79/jDfEQf2fDsPjMeNHRDGut0zXGZlxFbEkpIwM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=CMxK0oe/; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CMxK0oe/" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 564CxJin3836630; Fri, 4 Jul 2025 07:59:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1751633959; bh=f2A/NueUJIZRIX/TqU6PBtNEwqHhj1AcDC2S/EOzR/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CMxK0oe/lpovhvu16v8q6vM5zmDYNUwn6AQ1v85JfUYG+89fME43mP0RG+3Y3jiSM +TP8JVCgbf/ynzZ8dvT1x1t06j7/zmdmdjtGp4NAkN63CyiXgLwZdHIQA1XSG41f7v srojPBYJcA/AjRfdmeg5868mmzLqvG6B332s5YrY= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 564CxJ9Z2824756 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 4 Jul 2025 07:59:19 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 4 Jul 2025 07:59:19 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 4 Jul 2025 07:59:19 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 564CxIpO3049322; Fri, 4 Jul 2025 07:59:19 -0500 From: Devarsh Thakkar To: , , , CC: , , , , , , Subject: [PATCH v4 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine Date: Fri, 4 Jul 2025 18:29:15 +0530 Message-ID: <20250704125915.1224738-3-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250704125915.1224738-1-devarsht@ti.com> References: <20250704125915.1224738-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Do read-modify-write so that we re-use the characterized reset value as specified in TRM [1] to program calibration wait time which defines number of cycles to wait for after startup state machine is in bandgap enable state. This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's AM62L and J721E SoC since earlier calibration wait time was getting overwritten to zero value thus failing the PLL to lockup and causing timeout. [1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2): Link: https://www.ti.com/lit/pdf/spruj83 Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Signed-off-by: Devarsh Thakkar --- V4: No change V3: - Do read-modify-write to preserve reset value for calibration wait time V2: Introduced this as as separate patch drivers/phy/cadence/cdns-dphy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index da8de0a9d086..24a25606996c 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -30,6 +30,7 @@ #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) @@ -410,7 +411,8 @@ static int cdns_dphy_power_on(struct phy *phy) writel(reg, dphy->regs + DPHY_BAND_CFG); /* Start TX state machine. */ - writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, + reg = readl(dphy->regs + DPHY_CMN_SSM); + writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, dphy->regs + DPHY_CMN_SSM); ret = cdns_dphy_wait_for_pll_lock(dphy); -- 2.39.1