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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:58 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 07/16] clk: samsung: artpec-8: Add clock support for CMU_CORE block Date: Thu, 10 Jul 2025 09:20:37 +0900 Message-Id: <20250710002047.1573841-8-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_CORE Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c index 648abdd2f510..f41b7941c630 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -16,6 +16,7 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CMU_CMU_NR_CLK (DOUT_CLKCMU_VPP_CORE + 1) #define CMU_BUS_NR_CLK (DOUT_CLK_BUS_PCLK + 1) +#define CMU_CORE_NR_CLK (DOUT_CLK_CORE_PCLK + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) /* register offset definitions for cmu_cmu (0x12400000) */ @@ -476,6 +477,50 @@ static void __init artpec8_clk_cmu_bus_init(struct device_node *np) CLK_OF_DECLARE(artpec8_clk_cmu_bus, "axis,artpec8-cmu-bus", artpec8_clk_cmu_bus_init); +/* Register Offset definitions for CMU_CORE (0x12410000) */ +#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_CORE_DLP_USER 0x0120 +#define DIV_CLK_CORE_PCLK 0x1800 + +static const unsigned long cmu_core_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_CORE_ACLK_USER, + PLL_CON0_MUX_CLK_CORE_DLP_USER, + DIV_CLK_CORE_PCLK, +}; + +PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" }; +PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" }; + +static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = { + MUX(MOUT_CLK_CORE_ACLK_USER, "mout_clk_core_aclk_user", + mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1), + MUX(MOUT_CLK_CORE_DLP_USER, "mout_clk_core_dlp_user", + mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_core_div_clks[] __initconst = { + DIV(DOUT_CLK_CORE_PCLK, "dout_clk_core_pclk", + "mout_clk_core_aclk_user", DIV_CLK_CORE_PCLK, 0, 4), +}; + +static const struct samsung_cmu_info cmu_core_info __initconst = { + .mux_clks = cmu_core_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks), + .div_clks = cmu_core_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_core_div_clks), + .nr_clk_ids = CMU_CORE_NR_CLK, + .clk_regs = cmu_core_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs), +}; + +static void __init artpec8_clk_cmu_core_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_core_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_core, "axis,artpec8-cmu-core", + artpec8_clk_cmu_core_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 -- 2.34.1