From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FF132D3EDD for ; Fri, 11 Jul 2025 13:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240683; cv=none; b=tswQLvSNpwLVI7thOfQOAzo59uglr095UYFmB+ML02GFDHiaWUyE38RbC022xkCbLKkU5mS1E8+d5mrC/X/oz1YwlIFpAorHnmZJtrJP+zW1rVEodzP6Hs8fGrvBsbuPo1flqAdiq6ccKA4LMiNzlY6mWbgM+s0vsHtFRMqCmLQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240683; c=relaxed/simple; bh=3dUZhMseYubF72GaRbNm60DBdOGIBHybqo+w48PR4t4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GtbkjDTkIv9cs8BWp/FpVqUDnRvUqoJOtJsGD2BcOXmwGhB1fJOML4Dn0PBAeSlKZ8+/c34IQIp3s6g+WiCZjij9qGlGms6/vLjtyfMJSZdTlnLvNkWi3i1e6458a51wkEOxxdtPpL0Leu6jk6wCUxdgHSJCbrzp1iY6XiKbtew= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUYF8013847 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:34 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:34 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Date: Fri, 11 Jul 2025 21:30:17 +0800 Message-ID: <20250711133025.2192404-2-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 56BDUYF8013847 The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debc..61ceae0aa27a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP -- 2.34.1