From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9CF23B60C; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; cv=none; b=YwH23nsxRXKtQMwYjm3+M2JvDn77wqrHBsUALt/UJxJjQAFE2aLTMNT3L+KpOghuBHdwOOiR7qi68uh5uu0UIofa6FMjqwWEyQ3UOz8zyzfZ3KaFGMnDDoRB44m4FW3avdjiwpl1hZrOKXnhmWDSEf0YtEBBPJ5VqzWwrzJiwt4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752480028; c=relaxed/simple; bh=JWsCpgxekJacidLue+WK47HorDGR/FJsZcEgxYlPuFA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FgCdA93DIBPO7rykAVqi7UP/tZL9DUFbSGiciQJJf8x3ax8y1+ephsQ5UBtWbnFAW+8yQA9LnZzdtDSfFH2UEvLI3uif+lznuukCz9MXCA01I4bx8QMW6j+yXRLpOgrGdNA/dI0ynf5bHhrtq4wlgDNBYdaptk3hiZwwkg6jSJ0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SsWHKG2V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SsWHKG2V" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0CC9CC4CEF9; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752480028; bh=JWsCpgxekJacidLue+WK47HorDGR/FJsZcEgxYlPuFA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SsWHKG2VfLrNDRnFq2SpYGq13L3B63E9GyIaK15LFX6KJLVMsDV1xnICzky9sPJuE 6tsHQeXiiLND5vInv5rjbMsZARXfkjgP6J3x0PzWAPf+fvqHmD0/wXzkeZ9JNUvqS1 uRpSyZgmfWauEAoqi1SEKAQKr0VeruXka+hiJWAlbsJnAr/frPfiSub7J3xgtaU73L ehhU8vaklbAyCkFUIm568cyTBI/l1sl1+3+B1UFGG48h3uEKgSsNDgJdrp69bFObst 93BPpqvugss7j9QgdKBRKk2dVjoE/wgV7l6bxdilwVGwNSyHQ+TwnjBkjHQtpVrU/p DVFlCSsSPMT/Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 004EFC83F25; Mon, 14 Jul 2025 08:00:28 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Mon, 14 Jul 2025 15:59:19 +0800 Subject: [PATCH net-next 3/3] net: stmmac: Set CIC bit only for TX queues with COE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250714-xgmac-minor-fixes-v1-3-c34092a88a72@altera.com> References: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> In-Reply-To: <20250714-xgmac-minor-fixes-v1-0-c34092a88a72@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752480026; l=2519; i=rohan.g.thomas@altera.com; s=20250415; h=from:subject:message-id; bh=LvG0a5gBZ5g9VJhz1xFTiPD3FiH+GWS8NxcWQcWl6tc=; b=fVE9HlJaErdbIModd8D71uXp7Ny7wlJiiE+7BHU4coROJ/HaDD30Ly3V5zU8VBfqhYvYFE9wP g7WemhMLVucCOrtR+ZTEuvc3FgAK2dfr1Dr9e90L76eE7gmhl75xTAw X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=TLFM1xzY5sPOABaIaXHDNxCAiDwRegVWoy1tP842z5E= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250415 with auth_id=460 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Currently, in the AF_XDP transmit paths, the CIC bit of TX Desc3 is set for all packets. Setting this bit for packets transmitting through queues that don't support checksum offloading causes the TX DMA to get stuck after transmitting some packets. This patch ensures the CIC bit of TX Desc3 is set only if the TX queue supports checksum offloading. Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index f350a6662880a230a32ad6785c475cce4e950322..d9f7435a44fac695899e0b4ffd0dc7851c4e759f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2584,6 +2584,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue]; + bool csum = !priv->plat->tx_queues_cfg[queue].coe_unsupported; struct xsk_buff_pool *pool = tx_q->xsk_pool; unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc = NULL; @@ -2671,7 +2672,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) } stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdp_desc.len); stmmac_enable_dma_transmission(priv, priv->ioaddr, queue); @@ -4983,6 +4984,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, { struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue]; struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; + bool csum = !priv->plat->tx_queues_cfg[queue].coe_unsupported; unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; @@ -5034,7 +5036,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, stmmac_set_desc_addr(priv, tx_desc, dma_addr); stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdpf->len); tx_q->tx_count_frames++; -- 2.25.1