* [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller
@ 2025-07-15 12:14 dongxuyang
2025-07-15 12:15 ` [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: dongxuyang @ 2025-07-15 12:14 UTC (permalink / raw)
To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel
Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela, Xuyang Dong
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Updates:
dt-bindings: reset: eswin: Documentation for eic7700 SoC
v3 -> v4:
1. Remove register offsets in dt-bindings.
2. Changed the const value of "#reset-cells" from 2 to 1.
Because the offsets were removed from dt-bindings. There are
only IDs. And removed the description of it.
3. Modify copyright year from 2024 to 2025.
4. Redefined the IDs in the dt-bindings and used these to build a
reset array in reset driver. Ensure that the reset register and
reset value corresponding to the IDs are correct.
Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/
v2 -> v3:
1. Drop syscon and simple-mfd from yaml and code, because these are
not necessary.
2. Update description to introduce reset controller.
3. Add reset control indices for dt-bindings.
4. Keep the register offsets in dt-bindings.
Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/
v1 -> v2:
1. Clear warnings/errors for using "make dt_binding_check".
2. Update example, change parent node from sys-crg to reset-controller
for reset yaml.
3. Drop the child node and add '#reset-cells' to the parent node.
4. Drop the description, because sys-crg block is changed to reset-
controller.
5. Change hex numbers to decimal numbers going from 0, and drop the
not needed hardware numbers.
Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/
reset: eswin: Add eic7700 reset driver
v3 -> v4:
1. Add 'const' for the definition. It is 'const struct of_phandle_
args *reset_spec = data;'.
2. Modify copyright year from 2024 to 2025.
3. Included "eswin,eic7700-reset.h" in reset driver.
4. Added mapping table for reset IDs.
5. Removed of_xlate and idr functions as we are using IDs from DTS.
6. Removed .remove function.
Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/
v2 -> v3:
1. Change syscon_node_to_regmap() to MMIO regmap functions, because
dropped syscon.
2. Add BIT() in function eswin_reset_set() to shift the reset
control indices.
3. Remove forced type conversions from function eswin_reset_of_
xlate_lookup_id().
Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/
v1 -> v2:
1. Modify the code according to the suggestions.
2. Use eswin_reset_assert() and eswin_reset_deassert in function
eswin_reset_reset().
3. Place RESET_EIC7700 in Kconfig and Makefile in order.
4. Use dev_err_probe() in probe function.
Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/
Xuyang Dong (2):
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: eswin: Add eic7700 reset driver
.../bindings/reset/eswin,eic7700-reset.yaml | 42 ++
drivers/reset/Kconfig | 10 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-eic7700.c | 454 ++++++++++++++++++
.../dt-bindings/reset/eswin,eic7700-reset.h | 299 ++++++++++++
5 files changed, 806 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml
create mode 100644 drivers/reset/reset-eic7700.c
create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC 2025-07-15 12:14 [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang @ 2025-07-15 12:15 ` dongxuyang 2025-07-15 15:49 ` Krzysztof Kozlowski 2025-07-15 12:15 ` [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver dongxuyang 2025-07-15 15:47 ` [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski 2 siblings, 1 reply; 6+ messages in thread From: dongxuyang @ 2025-07-15 12:15 UTC (permalink / raw) To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela, Xuyang Dong From: Xuyang Dong <dongxuyang@eswincomputing.com> Add device tree binding documentation and header file for the ESWIN eic7700 reset controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- .../bindings/reset/eswin,eic7700-reset.yaml | 42 +++ .../dt-bindings/reset/eswin,eic7700-reset.h | 299 ++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h diff --git a/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml new file mode 100644 index 000000000000..d05a0531dce3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 SoC reset controller + +maintainers: + - Yifeng Huang <huangyifeng@eswincomputing.com> + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + The system reset controller can be used to reset various peripheral + controllers in ESWIN eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/eswin,eic7700-reset.h> + + reset-controller@51828000 { + compatible = "eswin,eic7700-reset"; + reg = <0x51828000 0x80000>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-bindings/reset/eswin,eic7700-reset.h new file mode 100644 index 000000000000..3450d04f04da --- /dev/null +++ b/include/dt-bindings/reset/eswin,eic7700-reset.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 reset controller. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __DT_ESWIN_EIC7700_RESET_H__ +#define __DT_ESWIN_EIC7700_RESET_H__ + +#define EIC7700_RESET_NOC_NSP 0 +#define EIC7700_RESET_NOC_CFG 1 +#define EIC7700_RESET_RNOC_NSP 2 +#define EIC7700_RESET_SNOC_TCU 3 +#define EIC7700_RESET_SNOC_U84 4 +#define EIC7700_RESET_SNOC_PCIE_XSR 5 +#define EIC7700_RESET_SNOC_PCIE_XMR 6 +#define EIC7700_RESET_SNOC_PCIE_PR 7 +#define EIC7700_RESET_SNOC_NPU 8 +#define EIC7700_RESET_SNOC_JTAG 9 +#define EIC7700_RESET_SNOC_DSP 10 +#define EIC7700_RESET_SNOC_DDRC1_P2 11 +#define EIC7700_RESET_SNOC_DDRC1_P1 12 +#define EIC7700_RESET_SNOC_DDRC0_P2 13 +#define EIC7700_RESET_SNOC_DDRC0_P1 14 +#define EIC7700_RESET_SNOC_D2D 15 +#define EIC7700_RESET_SNOC_AON 16 +#define EIC7700_RESET_GPU_AXI 17 +#define EIC7700_RESET_GPU_CFG 18 +#define EIC7700_RESET_GPU_GRAY 19 +#define EIC7700_RESET_GPU_JONES 20 +#define EIC7700_RESET_GPU_SPU 21 +#define EIC7700_RESET_DSP_AXI 22 +#define EIC7700_RESET_DSP_CFG 23 +#define EIC7700_RESET_DSP_DIV4 24 +#define EIC7700_RESET_DSP_DIV0 25 +#define EIC7700_RESET_DSP_DIV1 26 +#define EIC7700_RESET_DSP_DIV2 27 +#define EIC7700_RESET_DSP_DIV3 28 +#define EIC7700_RESET_D2D_AXI 29 +#define EIC7700_RESET_D2D_CFG 30 +#define EIC7700_RESET_D2D_PRST 31 +#define EIC7700_RESET_D2D_RAW_PCS 32 +#define EIC7700_RESET_D2D_RX 33 +#define EIC7700_RESET_D2D_TX 34 +#define EIC7700_RESET_D2D_CORE 35 +#define EIC7700_RESET_DDR1_ARST 36 +#define EIC7700_RESET_DDR1_TRACE 37 +#define EIC7700_RESET_DDR0_ARST 38 +#define EIC7700_RESET_DDR_CFG 39 +#define EIC7700_RESET_DDR0_TRACE 40 +#define EIC7700_RESET_DDR_CORE 41 +#define EIC7700_RESET_DDR_PRST 42 +#define EIC7700_RESET_TCU_AXI 43 +#define EIC7700_RESET_TCU_CFG 44 +#define EIC7700_RESET_TCU_TBU0 45 +#define EIC7700_RESET_TCU_TBU1 46 +#define EIC7700_RESET_TCU_TBU2 47 +#define EIC7700_RESET_TCU_TBU3 48 +#define EIC7700_RESET_TCU_TBU4 49 +#define EIC7700_RESET_TCU_TBU5 50 +#define EIC7700_RESET_TCU_TBU6 51 +#define EIC7700_RESET_TCU_TBU7 52 +#define EIC7700_RESET_TCU_TBU8 53 +#define EIC7700_RESET_TCU_TBU9 54 +#define EIC7700_RESET_TCU_TBU10 55 +#define EIC7700_RESET_TCU_TBU11 56 +#define EIC7700_RESET_TCU_TBU12 57 +#define EIC7700_RESET_TCU_TBU13 58 +#define EIC7700_RESET_TCU_TBU14 59 +#define EIC7700_RESET_TCU_TBU15 60 +#define EIC7700_RESET_TCU_TBU16 61 +#define EIC7700_RESET_NPU_AXI 62 +#define EIC7700_RESET_NPU_CFG 63 +#define EIC7700_RESET_NPU_CORE 64 +#define EIC7700_RESET_NPU_E31CORE 65 +#define EIC7700_RESET_NPU_E31BUS 66 +#define EIC7700_RESET_NPU_E31DBG 67 +#define EIC7700_RESET_NPU_LLC 68 +#define EIC7700_RESET_HSP_AXI 69 +#define EIC7700_RESET_HSP_CFG 70 +#define EIC7700_RESET_HSP_POR 71 +#define EIC7700_RESET_MSHC0_PHY 72 +#define EIC7700_RESET_MSHC1_PHY 73 +#define EIC7700_RESET_MSHC2_PHY 74 +#define EIC7700_RESET_MSHC0_TXRX 75 +#define EIC7700_RESET_MSHC1_TXRX 76 +#define EIC7700_RESET_MSHC2_TXRX 77 +#define EIC7700_RESET_SATA_ASIC0 78 +#define EIC7700_RESET_SATA_OOB 79 +#define EIC7700_RESET_SATA_PMALIVE 80 +#define EIC7700_RESET_SATA_RBC 81 +#define EIC7700_RESET_DMA0 82 +#define EIC7700_RESET_HSP_DMA 83 +#define EIC7700_RESET_USB0_VAUX 84 +#define EIC7700_RESET_USB1_VAUX 85 +#define EIC7700_RESET_HSP_SD1_PRST 86 +#define EIC7700_RESET_HSP_SD0_PRST 87 +#define EIC7700_RESET_HSP_EMMC_PRST 88 +#define EIC7700_RESET_HSP_DMA_PRST 89 +#define EIC7700_RESET_HSP_SD1_ARST 90 +#define EIC7700_RESET_HSP_SD0_ARST 91 +#define EIC7700_RESET_HSP_EMMC_ARST 92 +#define EIC7700_RESET_HSP_DMA_ARST 93 +#define EIC7700_RESET_HSP_ETH1_ARST 94 +#define EIC7700_RESET_HSP_ETH0_ARST 95 +#define EIC7700_RESET_SATA_ARST 96 +#define EIC7700_RESET_PCIE_CFG 97 +#define EIC7700_RESET_PCIE_POWEUP 98 +#define EIC7700_RESET_PCIE_PERST 99 +#define EIC7700_RESET_I2C0 100 +#define EIC7700_RESET_I2C1 101 +#define EIC7700_RESET_I2C2 102 +#define EIC7700_RESET_I2C3 103 +#define EIC7700_RESET_I2C4 104 +#define EIC7700_RESET_I2C5 105 +#define EIC7700_RESET_I2C6 106 +#define EIC7700_RESET_I2C7 107 +#define EIC7700_RESET_I2C8 108 +#define EIC7700_RESET_I2C9 109 +#define EIC7700_RESET_FAN 110 +#define EIC7700_RESET_PVT0 111 +#define EIC7700_RESET_PVT1 112 +#define EIC7700_RESET_MBOX0 113 +#define EIC7700_RESET_MBOX1 114 +#define EIC7700_RESET_MBOX2 115 +#define EIC7700_RESET_MBOX3 116 +#define EIC7700_RESET_MBOX4 117 +#define EIC7700_RESET_MBOX5 118 +#define EIC7700_RESET_MBOX6 119 +#define EIC7700_RESET_MBOX7 120 +#define EIC7700_RESET_MBOX8 121 +#define EIC7700_RESET_MBOX9 122 +#define EIC7700_RESET_MBOX10 123 +#define EIC7700_RESET_MBOX11 124 +#define EIC7700_RESET_MBOX12 125 +#define EIC7700_RESET_MBOX13 126 +#define EIC7700_RESET_MBOX14 127 +#define EIC7700_RESET_MBOX15 128 +#define EIC7700_RESET_UART0 129 +#define EIC7700_RESET_UART1 130 +#define EIC7700_RESET_UART2 131 +#define EIC7700_RESET_UART3 132 +#define EIC7700_RESET_UART4 133 +#define EIC7700_RESET_GPIO0 134 +#define EIC7700_RESET_GPIO1 135 +#define EIC7700_RESET_TIMER 136 +#define EIC7700_RESET_SSI0 137 +#define EIC7700_RESET_SSI1 138 +#define EIC7700_RESET_WDT0 139 +#define EIC7700_RESET_WDT1 140 +#define EIC7700_RESET_WDT2 141 +#define EIC7700_RESET_WDT3 142 +#define EIC7700_RESET_LSP_CFG 143 +#define EIC7700_RESET_U84_CORE0 144 +#define EIC7700_RESET_U84_CORE1 145 +#define EIC7700_RESET_U84_CORE2 146 +#define EIC7700_RESET_U84_CORE3 147 +#define EIC7700_RESET_U84_BUS 148 +#define EIC7700_RESET_U84_DBG 149 +#define EIC7700_RESET_U84_TRACECOM 150 +#define EIC7700_RESET_U84_TRACE0 151 +#define EIC7700_RESET_U84_TRACE1 152 +#define EIC7700_RESET_U84_TRACE2 153 +#define EIC7700_RESET_U84_TRACE3 154 +#define EIC7700_RESET_SCPU_CORE 155 +#define EIC7700_RESET_SCPU_BUS 156 +#define EIC7700_RESET_SCPU_DBG 157 +#define EIC7700_RESET_LPCPU_CORE 158 +#define EIC7700_RESET_LPCPU_BUS 159 +#define EIC7700_RESET_LPCPU_DBG 160 +#define EIC7700_RESET_VC_CFG 161 +#define EIC7700_RESET_VC_AXI 162 +#define EIC7700_RESET_VC_MONCFG 163 +#define EIC7700_RESET_JD_CFG 164 +#define EIC7700_RESET_JD_AXI 165 +#define EIC7700_RESET_JE_CFG 166 +#define EIC7700_RESET_JE_AXI 167 +#define EIC7700_RESET_VD_CFG 168 +#define EIC7700_RESET_VD_AXI 169 +#define EIC7700_RESET_VE_AXI 170 +#define EIC7700_RESET_VE_CFG 171 +#define EIC7700_RESET_G2D_CORE 172 +#define EIC7700_RESET_G2D_CFG 173 +#define EIC7700_RESET_G2D_AXI 174 +#define EIC7700_RESET_VI_AXI 175 +#define EIC7700_RESET_VI_CFG 176 +#define EIC7700_RESET_VI_DWE 177 +#define EIC7700_RESET_DVP 178 +#define EIC7700_RESET_ISP0 179 +#define EIC7700_RESET_ISP1 180 +#define EIC7700_RESET_SHUTTR0 181 +#define EIC7700_RESET_SHUTTR1 182 +#define EIC7700_RESET_SHUTTR2 183 +#define EIC7700_RESET_SHUTTR3 184 +#define EIC7700_RESET_SHUTTR4 185 +#define EIC7700_RESET_SHUTTR5 186 +#define EIC7700_RESET_VO_MIPI 187 +#define EIC7700_RESET_VO_PRST 188 +#define EIC7700_RESET_VO_HDMI_PRST 189 +#define EIC7700_RESET_VO_HDMI_PHY 190 +#define EIC7700_RESET_VO_HDMI 191 +#define EIC7700_RESET_VO_I2S 192 +#define EIC7700_RESET_VO_I2S_PRST 193 +#define EIC7700_RESET_VO_AXI 194 +#define EIC7700_RESET_VO_CFG 195 +#define EIC7700_RESET_VO_DC 196 +#define EIC7700_RESET_VO_DC_PRST 197 +#define EIC7700_RESET_BOOTSPI_HRST 198 +#define EIC7700_RESET_BOOTSPI 199 +#define EIC7700_RESET_ANO1 200 +#define EIC7700_RESET_ANO0 201 +#define EIC7700_RESET_DMA1_ARST 202 +#define EIC7700_RESET_DMA1_HRST 203 +#define EIC7700_RESET_FPRT 204 +#define EIC7700_RESET_HBLOCK 205 +#define EIC7700_RESET_SECSR 206 +#define EIC7700_RESET_OTP 207 +#define EIC7700_RESET_PKA 208 +#define EIC7700_RESET_SPACC 209 +#define EIC7700_RESET_TRNG 210 +#define EIC7700_RESET_TIMER0_0 211 +#define EIC7700_RESET_TIMER0_1 212 +#define EIC7700_RESET_TIMER0_2 213 +#define EIC7700_RESET_TIMER0_3 214 +#define EIC7700_RESET_TIMER0_4 215 +#define EIC7700_RESET_TIMER0_5 216 +#define EIC7700_RESET_TIMER0_6 217 +#define EIC7700_RESET_TIMER0_7 218 +#define EIC7700_RESET_TIMER0_N 219 +#define EIC7700_RESET_TIMER1_0 220 +#define EIC7700_RESET_TIMER1_1 221 +#define EIC7700_RESET_TIMER1_2 222 +#define EIC7700_RESET_TIMER1_3 223 +#define EIC7700_RESET_TIMER1_4 224 +#define EIC7700_RESET_TIMER1_5 225 +#define EIC7700_RESET_TIMER1_6 226 +#define EIC7700_RESET_TIMER1_7 227 +#define EIC7700_RESET_TIMER1_N 228 +#define EIC7700_RESET_TIMER2_0 229 +#define EIC7700_RESET_TIMER2_1 230 +#define EIC7700_RESET_TIMER2_2 231 +#define EIC7700_RESET_TIMER2_3 232 +#define EIC7700_RESET_TIMER2_4 233 +#define EIC7700_RESET_TIMER2_5 234 +#define EIC7700_RESET_TIMER2_6 235 +#define EIC7700_RESET_TIMER2_7 236 +#define EIC7700_RESET_TIMER2_N 237 +#define EIC7700_RESET_TIMER3_0 238 +#define EIC7700_RESET_TIMER3_1 239 +#define EIC7700_RESET_TIMER3_2 240 +#define EIC7700_RESET_TIMER3_3 241 +#define EIC7700_RESET_TIMER3_4 242 +#define EIC7700_RESET_TIMER3_5 243 +#define EIC7700_RESET_TIMER3_6 244 +#define EIC7700_RESET_TIMER3_7 245 +#define EIC7700_RESET_TIMER3_N 246 +#define EIC7700_RESET_RTC 247 +#define EIC7700_RESET_MNOC_SNOC_NSP 248 +#define EIC7700_RESET_MNOC_VC 249 +#define EIC7700_RESET_MNOC_CFG 250 +#define EIC7700_RESET_MNOC_HSP 251 +#define EIC7700_RESET_MNOC_GPU 252 +#define EIC7700_RESET_MNOC_DDRC1_P3 253 +#define EIC7700_RESET_MNOC_DDRC0_P3 254 +#define EIC7700_RESET_RNOC_VO 255 +#define EIC7700_RESET_RNOC_VI 256 +#define EIC7700_RESET_RNOC_SNOC_NSP 257 +#define EIC7700_RESET_RNOC_CFG 258 +#define EIC7700_RESET_MNOC_DDRC1_P4 259 +#define EIC7700_RESET_MNOC_DDRC0_P4 260 +#define EIC7700_RESET_CNOC_VO_CFG 261 +#define EIC7700_RESET_CNOC_VI_CFG 262 +#define EIC7700_RESET_CNOC_VC_CFG 263 +#define EIC7700_RESET_CNOC_TCU_CFG 264 +#define EIC7700_RESET_CNOC_PCIE_CFG 265 +#define EIC7700_RESET_CNOC_NPU_CFG 266 +#define EIC7700_RESET_CNOC_LSP_CFG 267 +#define EIC7700_RESET_CNOC_HSP_CFG 268 +#define EIC7700_RESET_CNOC_GPU_CFG 269 +#define EIC7700_RESET_CNOC_DSPT_CFG 270 +#define EIC7700_RESET_CNOC_DDRT1_CFG 271 +#define EIC7700_RESET_CNOC_DDRT0_CFG 272 +#define EIC7700_RESET_CNOC_D2D_CFG 273 +#define EIC7700_RESET_CNOC_CFG 274 +#define EIC7700_RESET_CNOC_CLMM_CFG 275 +#define EIC7700_RESET_CNOC_AON_CFG 276 +#define EIC7700_RESET_LNOC_CFG 277 +#define EIC7700_RESET_LNOC_NPU_LLC 278 +#define EIC7700_RESET_LNOC_DDRC1_P0 279 +#define EIC7700_RESET_LNOC_DDRC0_P0 280 +#define EIC7700_RESET_MAX 281 + +#endif /* __DT_ESWIN_EIC7700_RESET_H__ */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC 2025-07-15 12:15 ` [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang @ 2025-07-15 15:49 ` Krzysztof Kozlowski 0 siblings, 0 replies; 6+ messages in thread From: Krzysztof Kozlowski @ 2025-07-15 15:49 UTC (permalink / raw) To: dongxuyang, p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela On 15/07/2025 14:15, dongxuyang@eswincomputing.com wrote: > +#define EIC7700_RESET_LNOC_NPU_LLC 278 > +#define EIC7700_RESET_LNOC_DDRC1_P0 279 > +#define EIC7700_RESET_LNOC_DDRC0_P0 280 > +#define EIC7700_RESET_MAX 281 Drop, not binding usually. > + > +#endif /* __DT_ESWIN_EIC7700_RESET_H__ */ With above change: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- <form letter> This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions of patchset, under or above your Signed-off-by tag, unless patch changed significantly (e.g. new properties added to the DT bindings). Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. Full context and explanation: https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577 </form letter> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver 2025-07-15 12:14 [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang 2025-07-15 12:15 ` [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang @ 2025-07-15 12:15 ` dongxuyang 2025-07-15 13:37 ` Philipp Zabel 2025-07-15 15:47 ` [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski 2 siblings, 1 reply; 6+ messages in thread From: dongxuyang @ 2025-07-15 12:15 UTC (permalink / raw) To: p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela, Xuyang Dong From: Xuyang Dong <dongxuyang@eswincomputing.com> Add support for reset controller in eic7700 series chips. Provide functionality for asserting and deasserting resets on the chip. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/reset-eic7700.c | 454 ++++++++++++++++++++++++++++++++++ 3 files changed, 465 insertions(+) create mode 100644 drivers/reset/reset-eic7700.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d85be5899da6..82f829f4c9f0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,16 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_EIC7700 + bool "Reset controller driver for ESWIN SoCs" + depends on ARCH_ESWIN || COMPILE_TEST + default ARCH_ESWIN + help + This enables the reset controller driver for ESWIN SoCs. This driver is + specific to ESWIN SoCs and should only be enabled if using such hardware. + The driver supports eic7700 series chips and provides functionality for + asserting and deasserting resets on the chip. + config RESET_EYEQ bool "Mobileye EyeQ reset controller" depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 91e6348e3351..ceafbad0555c 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o obj-$(CONFIG_RESET_GPIO) += reset-gpio.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o diff --git a/drivers/reset/reset-eic7700.c b/drivers/reset/reset-eic7700.c new file mode 100644 index 000000000000..1acc531343b0 --- /dev/null +++ b/drivers/reset/reset-eic7700.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * ESWIN Reset Driver + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> +#include <linux/slab.h> +#include <linux/types.h> + +#include <dt-bindings/reset/eswin,eic7700-reset.h> + +#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0x30C +#define CLEAR_BOOT_FLAG_BIT BIT(0) +#define SYSCRG_RESET_OFFSET 0x400 + +/** + * struct eswin_reset_data - reset controller information structure + * @rcdev: reset controller entity + * @regmap: regmap handle containing the memory-mapped reset registers + */ +struct eswin_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const struct regmap_config eswin_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .max_register = 0x8000000, +}; + +struct eic7700_reg { + u32 reg; + u32 bit; +}; + +#define to_eswin_reset_data(p) container_of((p), struct eswin_reset_data, rcdev) + +#define EIC7700_RESET_OFFSET(id, reg, bit)[id] = \ + { SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) } + +/* mapping table for reset ID to register offset */ +static const struct eic7700_reg eic7700_register_offset[] = { + EIC7700_RESET_OFFSET(EIC7700_RESET_NOC_NSP, 0, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_NOC_CFG, 0, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_NSP, 0, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_TCU, 0, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_U84, 0, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_NPU, 0, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_JTAG, 0, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DSP, 0, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_D2D, 0, 15), + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_AON, 0, 16), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_AXI, 1, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_CFG, 1, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_GRAY, 1, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_JONES, 1, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_SPU, 1, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_AXI, 2, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_CFG, 2, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV4, 2, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV0, 2, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV1, 2, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV2, 2, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV3, 2, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_AXI, 3, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_CFG, 3, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_PRST, 3, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_RAW_PCS, 3, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_RX, 3, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_TX, 3, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_CORE, 3, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR1_ARST, 4, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR1_TRACE, 4, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR0_ARST, 4, 16), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_CFG, 4, 21), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR0_TRACE, 4, 22), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_CORE, 4, 23), + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_PRST, 4, 26), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_AXI, 5, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_CFG, 5, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU0, 5, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU1, 5, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU2, 5, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU3, 5, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU4, 5, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU5, 5, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU6, 5, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU7, 5, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU8, 5, 12), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU9, 5, 13), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU10, 5, 14), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU11, 5, 15), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU12, 5, 16), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU13, 5, 17), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU14, 5, 18), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU15, 5, 19), + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU16, 5, 20), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_AXI, 6, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_CFG, 6, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_CORE, 6, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31CORE, 6, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31BUS, 6, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31DBG, 6, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_LLC, 6, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_AXI, 7, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_CFG, 7, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_POR, 7, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC0_PHY, 7, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC1_PHY, 7, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC2_PHY, 7, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC0_TXRX, 7, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC1_TXRX, 7, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC2_TXRX, 7, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_ASIC0, 7, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_OOB, 7, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_PMALIVE, 7, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_RBC, 7, 12), + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA0, 7, 13), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA, 7, 14), + EIC7700_RESET_OFFSET(EIC7700_RESET_USB0_VAUX, 7, 15), + EIC7700_RESET_OFFSET(EIC7700_RESET_USB1_VAUX, 7, 16), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD1_PRST, 7, 17), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD0_PRST, 7, 18), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_EMMC_PRST, 7, 19), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA_PRST, 7, 20), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD1_ARST, 7, 21), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD0_ARST, 7, 22), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_EMMC_ARST, 7, 23), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA_ARST, 7, 24), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_ETH1_ARST, 7, 25), + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_ETH0_ARST, 7, 26), + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_ARST, 7, 27), + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_CFG, 8, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_POWEUP, 8, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_PERST, 8, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C0, 9, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C1, 9, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C2, 9, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C3, 9, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C4, 9, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C5, 9, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C6, 9, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C7, 9, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C8, 9, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C9, 9, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_FAN, 10, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_PVT0, 11, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_PVT1, 11, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX0, 12, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX1, 12, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX2, 12, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX3, 12, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX4, 12, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX5, 12, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX6, 12, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX7, 12, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX8, 12, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX9, 12, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX10, 12, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX11, 12, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX12, 12, 12), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX13, 12, 13), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX14, 12, 14), + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX15, 12, 15), + EIC7700_RESET_OFFSET(EIC7700_RESET_UART0, 13, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_UART1, 13, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_UART2, 13, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_UART3, 13, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_UART4, 13, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPIO0, 14, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_GPIO1, 14, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER, 15, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SSI0, 16, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SSI1, 16, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT0, 17, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT1, 17, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT2, 17, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT3, 17, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_LSP_CFG, 18, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE0, 19, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE1, 19, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE2, 19, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE3, 19, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_BUS, 19, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_DBG, 19, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACECOM, 19, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE0, 19, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE1, 19, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE2, 19, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE3, 19, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_CORE, 20, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_BUS, 20, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_DBG, 20, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_CORE, 21, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_BUS, 21, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_DBG, 21, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_CFG, 22, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_AXI, 22, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_MONCFG, 22, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_JD_CFG, 23, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_JD_AXI, 23, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_JE_CFG, 24, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_JE_AXI, 24, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VD_CFG, 25, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VD_AXI, 25, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VE_AXI, 26, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VE_CFG, 26, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_CORE, 27, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_CFG, 27, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_AXI, 27, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_AXI, 28, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_CFG, 28, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_DWE, 28, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_DVP, 29, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_ISP0, 30, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_ISP1, 31, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR0, 32, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR1, 32, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR2, 32, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR3, 32, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR4, 32, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR5, 32, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_MIPI, 33, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_PRST, 33, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI_PRST, 33, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI_PHY, 33, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI, 33, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_I2S, 34, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_I2S_PRST, 34, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_AXI, 35, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_CFG, 35, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_DC, 35, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_DC_PRST, 35, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_BOOTSPI_HRST, 36, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_BOOTSPI, 36, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_ANO1, 37, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_ANO0, 38, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA1_ARST, 39, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA1_HRST, 39, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_FPRT, 40, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_HBLOCK, 41, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SECSR, 42, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_OTP, 43, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_PKA, 44, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_SPACC, 45, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TRNG, 46, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_0, 48, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_1, 48, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_2, 48, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_3, 48, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_4, 48, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_5, 48, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_6, 48, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_7, 48, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_N, 48, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_0, 49, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_1, 49, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_2, 49, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_3, 49, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_4, 49, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_5, 49, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_6, 49, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_7, 49, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_N, 49, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_0, 50, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_1, 50, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_2, 50, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_3, 50, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_4, 50, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_5, 50, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_6, 50, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_7, 50, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_N, 50, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_0, 51, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_1, 51, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_2, 51, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_3, 51, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_4, 51, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_5, 51, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_6, 51, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_7, 51, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_N, 51, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_RTC, 52, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_SNOC_NSP, 53, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_VC, 53, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_CFG, 53, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_HSP, 53, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_GPU, 53, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC1_P3, 53, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC0_P3, 53, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_VO, 54, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_VI, 54, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_SNOC_NSP, 54, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_CFG, 54, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC1_P4, 54, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC0_P4, 54, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VO_CFG, 55, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VI_CFG, 55, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VC_CFG, 55, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_TCU_CFG, 55, 3), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_PCIE_CFG, 55, 4), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_NPU_CFG, 55, 5), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_LSP_CFG, 55, 6), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_HSP_CFG, 55, 7), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_GPU_CFG, 55, 8), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DSPT_CFG, 55, 9), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DDRT1_CFG, 55, 10), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DDRT0_CFG, 55, 11), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_D2D_CFG, 55, 12), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_CFG, 55, 13), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_CLMM_CFG, 55, 14), + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_AON_CFG, 55, 15), + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_CFG, 56, 0), + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_NPU_LLC, 56, 1), + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_DDRC1_P0, 56, 2), + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_DDRC0_P0, 56, 3), +}; + +/** + * eswin_reset_set() - program a device's reset + * @rcdev: reset controller entity + * @id: ID of the reset to toggle + * @assert: boolean flag to indicate assert or deassert + * + * This is a common internal function used to assert or deassert a device's + * reset by clear and set the reset bit. The device's reset is asserted if the + * @assert argument is true, or deasserted if @assert argument is false. + * + * Return: 0 for successful request, else a corresponding error value + */ +static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned long id, + bool assert) +{ + struct eswin_reset_data *data = to_eswin_reset_data(rcdev); + int ret; + + if (assert) + ret = regmap_clear_bits(data->regmap, + eic7700_register_offset[id].reg, + eic7700_register_offset[id].bit); + else + ret = regmap_set_bits(data->regmap, + eic7700_register_offset[id].reg, + eic7700_register_offset[id].bit); + + return ret; +} + +static int eswin_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return eswin_reset_set(rcdev, id, true); +} + +static int eswin_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return eswin_reset_set(rcdev, id, false); +} + +static int eswin_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = eswin_reset_assert(rcdev, id); + if (ret) + return ret; + + return eswin_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops eswin_reset_ops = { + .reset = eswin_reset_reset, + .assert = eswin_reset_assert, + .deassert = eswin_reset_deassert, +}; + +static const struct of_device_id eswin_reset_dt_ids[] = { + { + .compatible = "eswin,eic7700-reset", + }, + { /* sentinel */ } +}; + +static int eswin_reset_probe(struct platform_device *pdev) +{ + struct eswin_reset_data *data; + struct device *dev = &pdev->dev; + void __iomem *base; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + data->regmap = devm_regmap_init_mmio(dev, base, &eswin_regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), + "failed to get regmap!\n"); + + platform_set_drvdata(pdev, data); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &eswin_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + data->rcdev.of_reset_n_cells = 1; + data->rcdev.dev = &pdev->dev; + data->rcdev.nr_resets = EIC7700_RESET_MAX; + + /* clear boot flag so u84 and scpu could be reseted by software */ + regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET, + CLEAR_BOOT_FLAG_BIT); + msleep(50); + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static struct platform_driver eswin_reset_driver = { + .probe = eswin_reset_probe, + .driver = { + .name = "eswin-reset", + .of_match_table = eswin_reset_dt_ids, + }, +}; + +static int __init eswin_reset_init(void) +{ + return platform_driver_register(&eswin_reset_driver); +} +arch_initcall(eswin_reset_init); -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver 2025-07-15 12:15 ` [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver dongxuyang @ 2025-07-15 13:37 ` Philipp Zabel 0 siblings, 0 replies; 6+ messages in thread From: Philipp Zabel @ 2025-07-15 13:37 UTC (permalink / raw) To: dongxuyang, robh, krzk+dt, conor+dt, devicetree, linux-kernel Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela On Di, 2025-07-15 at 20:15 +0800, dongxuyang@eswincomputing.com wrote: > From: Xuyang Dong <dongxuyang@eswincomputing.com> > > Add support for reset controller in eic7700 series chips. > Provide functionality for asserting and deasserting resets > on the chip. > > Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> > Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> > --- > drivers/reset/Kconfig | 10 + > drivers/reset/Makefile | 1 + > drivers/reset/reset-eic7700.c | 454 ++++++++++++++++++++++++++++++++++ > 3 files changed, 465 insertions(+) > create mode 100644 drivers/reset/reset-eic7700.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index d85be5899da6..82f829f4c9f0 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -66,6 +66,16 @@ config RESET_BRCMSTB_RESCAL > This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on > BCM7216. > > +config RESET_EIC7700 > + bool "Reset controller driver for ESWIN SoCs" > + depends on ARCH_ESWIN || COMPILE_TEST > + default ARCH_ESWIN > + help > + This enables the reset controller driver for ESWIN SoCs. This driver is > + specific to ESWIN SoCs and should only be enabled if using such hardware. > + The driver supports eic7700 series chips and provides functionality for > + asserting and deasserting resets on the chip. > + > config RESET_EYEQ > bool "Mobileye EyeQ reset controller" > depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 91e6348e3351..ceafbad0555c 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o > obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o > obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o > obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o > +obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o > obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o > obj-$(CONFIG_RESET_GPIO) += reset-gpio.o > obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o > diff --git a/drivers/reset/reset-eic7700.c b/drivers/reset/reset-eic7700.c > new file mode 100644 > index 000000000000..1acc531343b0 > --- /dev/null > +++ b/drivers/reset/reset-eic7700.c > @@ -0,0 +1,454 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. > + * All rights reserved. > + * > + * ESWIN Reset Driver > + * > + * Authors: > + * Yifeng Huang <huangyifeng@eswincomputing.com> > + * Xuyang Dong <dongxuyang@eswincomputing.com> > + */ > + > +#include <linux/err.h> > +#include <linux/init.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/reset-controller.h> > +#include <linux/slab.h> > +#include <linux/types.h> > + > +#include <dt-bindings/reset/eswin,eic7700-reset.h> > + > +#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0x30C > +#define CLEAR_BOOT_FLAG_BIT BIT(0) > +#define SYSCRG_RESET_OFFSET 0x400 > + > +/** > + * struct eswin_reset_data - reset controller information structure > + * @rcdev: reset controller entity > + * @regmap: regmap handle containing the memory-mapped reset registers > + */ > +struct eswin_reset_data { > + struct reset_controller_dev rcdev; > + struct regmap *regmap; > +}; > + > +static const struct regmap_config eswin_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .max_register = 0x8000000, That doesn't look correct. According to the device tree example, the register space is only 0x80000 bytes. This should be the address offset of the last valid register, so I'd expect at most 0x7fffc. > +}; > + > +struct eic7700_reg { > + u32 reg; > + u32 bit; > +}; > + > +#define to_eswin_reset_data(p) container_of((p), struct eswin_reset_data, rcdev) Please make this an inline function. > + > +#define EIC7700_RESET_OFFSET(id, reg, bit)[id] = \ > + { SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) } I suggest calling this macro EIC7700_RESET(). It's shorter and the "bit" field is not an offset. > + > +/* mapping table for reset ID to register offset */ > +static const struct eic7700_reg eic7700_register_offset[] = { You could make this eic7700_register_offset[EIC7700_RESET_MAX]. Same as above, there might be a better name than _register_offset. How about eic7700_resets[]? > + EIC7700_RESET_OFFSET(EIC7700_RESET_NOC_NSP, 0, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NOC_CFG, 0, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_NSP, 0, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_TCU, 0, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_U84, 0, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_NPU, 0, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_JTAG, 0, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DSP, 0, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_D2D, 0, 15), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SNOC_AON, 0, 16), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_AXI, 1, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_CFG, 1, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_GRAY, 1, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_JONES, 1, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPU_SPU, 1, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_AXI, 2, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_CFG, 2, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV4, 2, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV0, 2, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV1, 2, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV2, 2, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DSP_DIV3, 2, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_AXI, 3, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_CFG, 3, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_PRST, 3, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_RAW_PCS, 3, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_RX, 3, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_TX, 3, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_D2D_CORE, 3, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR1_ARST, 4, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR1_TRACE, 4, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR0_ARST, 4, 16), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_CFG, 4, 21), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR0_TRACE, 4, 22), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_CORE, 4, 23), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DDR_PRST, 4, 26), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_AXI, 5, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_CFG, 5, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU0, 5, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU1, 5, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU2, 5, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU3, 5, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU4, 5, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU5, 5, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU6, 5, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU7, 5, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU8, 5, 12), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU9, 5, 13), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU10, 5, 14), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU11, 5, 15), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU12, 5, 16), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU13, 5, 17), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU14, 5, 18), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU15, 5, 19), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TCU_TBU16, 5, 20), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_AXI, 6, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_CFG, 6, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_CORE, 6, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31CORE, 6, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31BUS, 6, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_E31DBG, 6, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_NPU_LLC, 6, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_AXI, 7, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_CFG, 7, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_POR, 7, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC0_PHY, 7, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC1_PHY, 7, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC2_PHY, 7, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC0_TXRX, 7, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC1_TXRX, 7, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MSHC2_TXRX, 7, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_ASIC0, 7, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_OOB, 7, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_PMALIVE, 7, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_RBC, 7, 12), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA0, 7, 13), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA, 7, 14), > + EIC7700_RESET_OFFSET(EIC7700_RESET_USB0_VAUX, 7, 15), > + EIC7700_RESET_OFFSET(EIC7700_RESET_USB1_VAUX, 7, 16), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD1_PRST, 7, 17), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD0_PRST, 7, 18), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_EMMC_PRST, 7, 19), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA_PRST, 7, 20), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD1_ARST, 7, 21), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_SD0_ARST, 7, 22), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_EMMC_ARST, 7, 23), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_DMA_ARST, 7, 24), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_ETH1_ARST, 7, 25), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HSP_ETH0_ARST, 7, 26), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SATA_ARST, 7, 27), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_CFG, 8, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_POWEUP, 8, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PCIE_PERST, 8, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C0, 9, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C1, 9, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C2, 9, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C3, 9, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C4, 9, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C5, 9, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C6, 9, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C7, 9, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C8, 9, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_I2C9, 9, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_FAN, 10, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PVT0, 11, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PVT1, 11, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX0, 12, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX1, 12, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX2, 12, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX3, 12, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX4, 12, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX5, 12, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX6, 12, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX7, 12, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX8, 12, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX9, 12, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX10, 12, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX11, 12, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX12, 12, 12), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX13, 12, 13), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX14, 12, 14), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MBOX15, 12, 15), > + EIC7700_RESET_OFFSET(EIC7700_RESET_UART0, 13, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_UART1, 13, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_UART2, 13, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_UART3, 13, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_UART4, 13, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPIO0, 14, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_GPIO1, 14, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER, 15, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SSI0, 16, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SSI1, 16, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT0, 17, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT1, 17, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT2, 17, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_WDT3, 17, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LSP_CFG, 18, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE0, 19, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE1, 19, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE2, 19, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_CORE3, 19, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_BUS, 19, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_DBG, 19, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACECOM, 19, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE0, 19, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE1, 19, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE2, 19, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_U84_TRACE3, 19, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_CORE, 20, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_BUS, 20, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SCPU_DBG, 20, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_CORE, 21, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_BUS, 21, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LPCPU_DBG, 21, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_CFG, 22, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_AXI, 22, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VC_MONCFG, 22, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_JD_CFG, 23, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_JD_AXI, 23, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_JE_CFG, 24, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_JE_AXI, 24, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VD_CFG, 25, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VD_AXI, 25, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VE_AXI, 26, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VE_CFG, 26, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_CORE, 27, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_CFG, 27, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_G2D_AXI, 27, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_AXI, 28, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_CFG, 28, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VI_DWE, 28, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DVP, 29, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_ISP0, 30, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_ISP1, 31, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR0, 32, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR1, 32, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR2, 32, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR3, 32, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR4, 32, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SHUTTR5, 32, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_MIPI, 33, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_PRST, 33, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI_PRST, 33, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI_PHY, 33, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_HDMI, 33, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_I2S, 34, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_I2S_PRST, 34, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_AXI, 35, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_CFG, 35, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_DC, 35, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_VO_DC_PRST, 35, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_BOOTSPI_HRST, 36, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_BOOTSPI, 36, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_ANO1, 37, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_ANO0, 38, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA1_ARST, 39, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_DMA1_HRST, 39, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_FPRT, 40, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_HBLOCK, 41, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SECSR, 42, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_OTP, 43, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_PKA, 44, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_SPACC, 45, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TRNG, 46, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_0, 48, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_1, 48, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_2, 48, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_3, 48, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_4, 48, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_5, 48, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_6, 48, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_7, 48, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER0_N, 48, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_0, 49, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_1, 49, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_2, 49, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_3, 49, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_4, 49, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_5, 49, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_6, 49, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_7, 49, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER1_N, 49, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_0, 50, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_1, 50, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_2, 50, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_3, 50, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_4, 50, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_5, 50, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_6, 50, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_7, 50, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER2_N, 50, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_0, 51, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_1, 51, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_2, 51, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_3, 51, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_4, 51, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_5, 51, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_6, 51, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_7, 51, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_TIMER3_N, 51, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RTC, 52, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_SNOC_NSP, 53, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_VC, 53, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_CFG, 53, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_HSP, 53, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_GPU, 53, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC1_P3, 53, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC0_P3, 53, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_VO, 54, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_VI, 54, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_SNOC_NSP, 54, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_RNOC_CFG, 54, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC1_P4, 54, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_MNOC_DDRC0_P4, 54, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VO_CFG, 55, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VI_CFG, 55, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_VC_CFG, 55, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_TCU_CFG, 55, 3), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_PCIE_CFG, 55, 4), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_NPU_CFG, 55, 5), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_LSP_CFG, 55, 6), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_HSP_CFG, 55, 7), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_GPU_CFG, 55, 8), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DSPT_CFG, 55, 9), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DDRT1_CFG, 55, 10), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_DDRT0_CFG, 55, 11), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_D2D_CFG, 55, 12), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_CFG, 55, 13), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_CLMM_CFG, 55, 14), > + EIC7700_RESET_OFFSET(EIC7700_RESET_CNOC_AON_CFG, 55, 15), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_CFG, 56, 0), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_NPU_LLC, 56, 1), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_DDRC1_P0, 56, 2), > + EIC7700_RESET_OFFSET(EIC7700_RESET_LNOC_DDRC0_P0, 56, 3), > +}; > + > +/** > + * eswin_reset_set() - program a device's reset > + * @rcdev: reset controller entity > + * @id: ID of the reset to toggle > + * @assert: boolean flag to indicate assert or deassert > + * > + * This is a common internal function used to assert or deassert a device's > + * reset by clear and set the reset bit. The device's reset is asserted if the > + * @assert argument is true, or deasserted if @assert argument is false. > + * > + * Return: 0 for successful request, else a corresponding error value > + */ > +static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned long id, > + bool assert) > +{ > + struct eswin_reset_data *data = to_eswin_reset_data(rcdev); > + int ret; > + > + if (assert) > + ret = regmap_clear_bits(data->regmap, > + eic7700_register_offset[id].reg, > + eic7700_register_offset[id].bit); > + else > + ret = regmap_set_bits(data->regmap, > + eic7700_register_offset[id].reg, > + eic7700_register_offset[id].bit); > + > + return ret; > +} Please just fold this into the eswin_reset_assert/deassert() functions. There is no need to have a common helper function where the only common line of code is the data variable assignment. > + > +static int eswin_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return eswin_reset_set(rcdev, id, true); > +} > + > +static int eswin_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return eswin_reset_set(rcdev, id, false); > +} > + > +static int eswin_reset_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + int ret; > + > + ret = eswin_reset_assert(rcdev, id); > + if (ret) > + return ret; Does this work without delay for every IP core contained in this SoC? > + return eswin_reset_deassert(rcdev, id); > +} > + > +static const struct reset_control_ops eswin_reset_ops = { > + .reset = eswin_reset_reset, > + .assert = eswin_reset_assert, > + .deassert = eswin_reset_deassert, > +}; > + > +static const struct of_device_id eswin_reset_dt_ids[] = { > + { > + .compatible = "eswin,eic7700-reset", > + }, > + { /* sentinel */ } > +}; > + > +static int eswin_reset_probe(struct platform_device *pdev) > +{ > + struct eswin_reset_data *data; > + struct device *dev = &pdev->dev; > + void __iomem *base; > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + data->regmap = devm_regmap_init_mmio(dev, base, &eswin_regmap_config); > + if (IS_ERR(data->regmap)) > + return dev_err_probe(dev, PTR_ERR(data->regmap), > + "failed to get regmap!\n"); > + > + platform_set_drvdata(pdev, data); > + > + data->rcdev.owner = THIS_MODULE; > + data->rcdev.ops = &eswin_reset_ops; > + data->rcdev.of_node = pdev->dev.of_node; > + data->rcdev.of_reset_n_cells = 1; > + data->rcdev.dev = &pdev->dev; > + data->rcdev.nr_resets = EIC7700_RESET_MAX; Better use ARRAY_SIZE(eic7700_register_offset). > + > + /* clear boot flag so u84 and scpu could be reseted by software */ > + regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET, > + CLEAR_BOOT_FLAG_BIT); > + msleep(50); > + > + return devm_reset_controller_register(&pdev->dev, &data->rcdev); > +} > + > +static struct platform_driver eswin_reset_driver = { > + .probe = eswin_reset_probe, > + .driver = { > + .name = "eswin-reset", > + .of_match_table = eswin_reset_dt_ids, > + }, > +}; > + > +static int __init eswin_reset_init(void) > +{ > + return platform_driver_register(&eswin_reset_driver); > +} > +arch_initcall(eswin_reset_init); Why does this have to be arch_initcall()? regards Philipp ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller 2025-07-15 12:14 [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang 2025-07-15 12:15 ` [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang 2025-07-15 12:15 ` [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver dongxuyang @ 2025-07-15 15:47 ` Krzysztof Kozlowski 2 siblings, 0 replies; 6+ messages in thread From: Krzysztof Kozlowski @ 2025-07-15 15:47 UTC (permalink / raw) To: dongxuyang, p.zabel, robh, krzk+dt, conor+dt, devicetree, linux-kernel Cc: ningyu, linmin, huangyifeng, pinkesh.vaghela On 15/07/2025 14:14, dongxuyang@eswincomputing.com wrote: > From: Xuyang Dong <dongxuyang@eswincomputing.com> > > Updates: > > dt-bindings: reset: eswin: Documentation for eic7700 SoC > v3 -> v4: > 1. Remove register offsets in dt-bindings. > 2. Changed the const value of "#reset-cells" from 2 to 1. > Because the offsets were removed from dt-bindings. There are > only IDs. And removed the description of it. > 3. Modify copyright year from 2024 to 2025. > 4. Redefined the IDs in the dt-bindings and used these to build a > reset array in reset driver. Ensure that the reset register and > reset value corresponding to the IDs are correct. > Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/ This leads to clock patchset, not reset. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-07-15 15:49 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-15 12:14 [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller dongxuyang 2025-07-15 12:15 ` [PATCH v4 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC dongxuyang 2025-07-15 15:49 ` Krzysztof Kozlowski 2025-07-15 12:15 ` [PATCH v4 2/2] reset: eswin: Add eic7700 reset driver dongxuyang 2025-07-15 13:37 ` Philipp Zabel 2025-07-15 15:47 ` [PATCH v4 0/2] Add driver support for ESWIN eic7700 SoC reset controller Krzysztof Kozlowski
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