* [GIT PULL] irqchip: Add GICv5 support
@ 2025-07-17 12:23 Marc Zyngier
2025-07-18 21:26 ` Thomas Gleixner
0 siblings, 1 reply; 3+ messages in thread
From: Marc Zyngier @ 2025-07-17 12:23 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Breno Leitao, Catalin Marinas, Conor Dooley, Jonathan Cameron,
Krzysztof Kozlowski, Lorenzo Pieralisi, Mark Rutland, Rob Herring,
Sascha Bischoff, Timothy Hayes, Will Deacon, Oliver Upton,
linux-kernel, linux-arm-kernel, kvmarm
Thomas,
After some time simmering in -next without much catching fire (only a
single regression has been reported, which was promptly fixed), here's
the pull request for the GICv5 core infrastructure.
There are still a couple of patches on the list (mostly addressing
error paths, and actively being reviewed), but I don't see anything
that would warrant holding this any longer, and these fixes can be
added down the line. If anything, this work has allowed us to
pipe-clean a number of issues in the tree.
Please note that the kvmarm tree also carries this branch, as this is
a dependency for enabling GICv3 compatibility for guests on a GICv5
host.
Please pull,
M.
The following changes since commit 86731a2a651e58953fc949573895f2fa6d456841:
Linux 6.16-rc3 (2025-06-22 13:30:08 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-gic-v5-host
for you to fetch changes up to 65a5520a27570787b17e6f0b093829fc7e0514e2:
arm64: smp: Fix pNMI setup after GICv5 rework (2025-07-15 18:11:12 +0100)
----------------------------------------------------------------
GICv5 initial host support
Add host kernel support for the new arm64 GICv5 architecture, which is
quite a departure from the previous ones.
Include support for the full gamut of the architecture (interrupt
routing and delivery to CPUs, wired interrupts, MSIs, and interrupt
translation).
----------------------------------------------------------------
Lorenzo Pieralisi (30):
dt-bindings: interrupt-controller: Add Arm GICv5
arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1
arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1
arm64/sysreg: Add ICC_ICSR_EL1
arm64/sysreg: Add ICC_PPI_HMR<n>_EL1
arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1
arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1
arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1
arm64/sysreg: Add ICC_CR0_EL1
arm64/sysreg: Add ICC_PCR_EL1
arm64/sysreg: Add ICC_IDR0_EL1
arm64/sysreg: Add ICH_HFGRTR_EL2
arm64/sysreg: Add ICH_HFGWTR_EL2
arm64/sysreg: Add ICH_HFGITR_EL2
arm64: Disable GICv5 read/write/instruction traps
arm64: cpucaps: Rename GICv3 CPU interface capability
arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability
arm64: Add support for GICv5 GSB barriers
irqchip/gic-v5: Add GICv5 PPI support
irqchip/gic-v5: Add GICv5 IRS/SPI support
irqchip/gic-v5: Add GICv5 LPI/IPI support
irqchip/gic-v5: Enable GICv5 SMP booting
of/irq: Add of_msi_xlate() helper function
PCI/MSI: Add pci_msi_map_rid_ctlr_node() helper function
irqchip/gic-v3: Rename GICv3 ITS MSI parent
irqchip/msi-lib: Add IRQ_DOMAIN_FLAG_FWNODE_PARENT handling
irqchip/gic-v5: Add GICv5 ITS support
irqchip/gic-v5: Add GICv5 IWB support
docs: arm64: gic-v5: Document booting requirements for GICv5
arm64: Kconfig: Enable GICv5
Marc Zyngier (2):
arm64: smp: Support non-SGIs for IPIs
arm64: smp: Fix pNMI setup after GICv5 rework
Documentation/arch/arm64/booting.rst | 41 +
.../interrupt-controller/arm,gic-v5-iwb.yaml | 78 ++
.../bindings/interrupt-controller/arm,gic-v5.yaml | 267 +++++
MAINTAINERS | 10 +
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/barrier.h | 3 +
arch/arm64/include/asm/el2_setup.h | 45 +
arch/arm64/include/asm/smp.h | 24 +-
arch/arm64/include/asm/sysreg.h | 71 +-
arch/arm64/kernel/cpufeature.c | 17 +-
arch/arm64/kernel/smp.c | 142 ++-
arch/arm64/tools/cpucaps | 3 +-
arch/arm64/tools/sysreg | 495 +++++++-
drivers/irqchip/Kconfig | 12 +
drivers/irqchip/Makefile | 5 +-
drivers/irqchip/irq-gic-common.h | 2 -
...3-its-msi-parent.c => irq-gic-its-msi-parent.c} | 168 ++-
drivers/irqchip/irq-gic-its-msi-parent.h | 12 +
drivers/irqchip/irq-gic-v3-its.c | 1 +
drivers/irqchip/irq-gic-v5-irs.c | 822 +++++++++++++
drivers/irqchip/irq-gic-v5-its.c | 1228 ++++++++++++++++++++
drivers/irqchip/irq-gic-v5-iwb.c | 284 +++++
drivers/irqchip/irq-gic-v5.c | 1087 +++++++++++++++++
drivers/irqchip/irq-gic.c | 2 +-
drivers/irqchip/irq-msi-lib.c | 5 +-
drivers/of/irq.c | 22 +-
drivers/pci/msi/irqdomain.c | 20 +
include/asm-generic/msi.h | 1 +
include/linux/irqchip/arm-gic-v5.h | 394 +++++++
include/linux/irqdomain.h | 3 +
include/linux/msi.h | 1 +
include/linux/of_irq.h | 5 +
32 files changed, 5199 insertions(+), 72 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb.yaml
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
rename drivers/irqchip/{irq-gic-v3-its-msi-parent.c => irq-gic-its-msi-parent.c} (59%)
create mode 100644 drivers/irqchip/irq-gic-its-msi-parent.h
create mode 100644 drivers/irqchip/irq-gic-v5-irs.c
create mode 100644 drivers/irqchip/irq-gic-v5-its.c
create mode 100644 drivers/irqchip/irq-gic-v5-iwb.c
create mode 100644 drivers/irqchip/irq-gic-v5.c
create mode 100644 include/linux/irqchip/arm-gic-v5.h
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [GIT PULL] irqchip: Add GICv5 support
2025-07-17 12:23 [GIT PULL] irqchip: Add GICv5 support Marc Zyngier
@ 2025-07-18 21:26 ` Thomas Gleixner
2025-07-19 7:32 ` Marc Zyngier
0 siblings, 1 reply; 3+ messages in thread
From: Thomas Gleixner @ 2025-07-18 21:26 UTC (permalink / raw)
To: Marc Zyngier
Cc: Breno Leitao, Catalin Marinas, Conor Dooley, Jonathan Cameron,
Krzysztof Kozlowski, Lorenzo Pieralisi, Mark Rutland, Rob Herring,
Sascha Bischoff, Timothy Hayes, Will Deacon, Oliver Upton,
linux-kernel, linux-arm-kernel, kvmarm
Marc!
On Thu, Jul 17 2025 at 13:23, Marc Zyngier wrote:
> Thomas,
>
> After some time simmering in -next without much catching fire (only a
> single regression has been reported, which was promptly fixed), here's
> the pull request for the GICv5 core infrastructure.
>
> There are still a couple of patches on the list (mostly addressing
> error paths, and actively being reviewed), but I don't see anything
> that would warrant holding this any longer, and these fixes can be
> added down the line. If anything, this work has allowed us to
> pipe-clean a number of issues in the tree.
>
> Please note that the kvmarm tree also carries this branch, as this is
> a dependency for enabling GICv3 compatibility for guests on a GICv5
> host.
I'm fine with keeping this in the kvmarm tree only if that is intended
to hit the next merge window. There is no point to carry this
redundantly in two trees, unless there is some conflict to resolve in my
tree.
If the kvmarm stuff is not ready yet, then please let me know and I
happily pull in the pile.
Thanks,
tglx
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [GIT PULL] irqchip: Add GICv5 support
2025-07-18 21:26 ` Thomas Gleixner
@ 2025-07-19 7:32 ` Marc Zyngier
0 siblings, 0 replies; 3+ messages in thread
From: Marc Zyngier @ 2025-07-19 7:32 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Breno Leitao, Catalin Marinas, Conor Dooley, Jonathan Cameron,
Krzysztof Kozlowski, Lorenzo Pieralisi, Mark Rutland, Rob Herring,
Sascha Bischoff, Timothy Hayes, Will Deacon, Oliver Upton,
linux-kernel, linux-arm-kernel, kvmarm
On Fri, 18 Jul 2025 22:26:58 +0100,
Thomas Gleixner <tglx@linutronix.de> wrote:
>
> Marc!
>
> On Thu, Jul 17 2025 at 13:23, Marc Zyngier wrote:
>
> > Thomas,
> >
> > After some time simmering in -next without much catching fire (only a
> > single regression has been reported, which was promptly fixed), here's
> > the pull request for the GICv5 core infrastructure.
> >
> > There are still a couple of patches on the list (mostly addressing
> > error paths, and actively being reviewed), but I don't see anything
> > that would warrant holding this any longer, and these fixes can be
> > added down the line. If anything, this work has allowed us to
> > pipe-clean a number of issues in the tree.
> >
> > Please note that the kvmarm tree also carries this branch, as this is
> > a dependency for enabling GICv3 compatibility for guests on a GICv5
> > host.
>
> I'm fine with keeping this in the kvmarm tree only if that is intended
> to hit the next merge window. There is no point to carry this
> redundantly in two trees, unless there is some conflict to resolve in my
> tree.
Thanks for that, I'll keep the branch around anyway, should you need
to pull it to resolve some last minute conflict.
> If the kvmarm stuff is not ready yet, then please let me know and I
> happily pull in the pile.
The kvmarm stuff is ready to go, has been simmering in -next for the
same time, and is also aiming for 6.17.
Thanks again,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-07-19 7:32 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-17 12:23 [GIT PULL] irqchip: Add GICv5 support Marc Zyngier
2025-07-18 21:26 ` Thomas Gleixner
2025-07-19 7:32 ` Marc Zyngier
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).